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## Module aarch64

1.59.0 · Source
Available on AArch64 or ARM64EC only.
Expand description

Platform-specific intrinsics for the `aarch64` platform.

See the module documentation for more details.

## Structs§

float16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of four packed `f16`.
float16x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `float16x4_t` vectors.
float16x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `float16x4_t` vectors.
float16x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `float16x4_t` vectors.
float16x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of eight packed `f16`.
float16x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `float16x8_t` vectors.
float16x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `float16x8_t` vectors.
float16x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `float16x8_t` vectors.
float32x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of two packed `f32`.
float32x2x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `float32x2_t` vectors.
float32x2x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `float32x2_t` vectors.
float32x2x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `float32x2_t` vectors.
float32x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of four packed `f32`.
float32x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `float32x4_t` vectors.
float32x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `float32x4_t` vectors.
float32x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `float32x4_t` vectors.
float64x1_t
  ARM-specific 64-bit wide vector of one packed `f64`.
float64x1x2_t
  ARM-specific type containing two `float64x1_t` vectors.
float64x1x3_t
  ARM-specific type containing three `float64x1_t` vectors.
float64x1x4_t
  ARM-specific type containing four `float64x1_t` vectors.
float64x2_t
  ARM-specific 128-bit wide vector of two packed `f64`.
float64x2x2_t
  ARM-specific type containing two `float64x2_t` vectors.
float64x2x3_t
  ARM-specific type containing three `float64x2_t` vectors.
float64x2x4_t
  ARM-specific type containing four `float64x2_t` vectors.
int8x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of eight packed `i8`.
int8x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int8x8_t` vectors.
int8x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int8x8_t` vectors.
int8x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int8x8_t` vectors.
int8x16_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of sixteen packed `i8`.
int8x16x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int8x16_t` vectors.
int8x16x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int8x16_t` vectors.
int8x16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int8x16_t` vectors.
int16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of four packed `i16`.
int16x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int16x4_t` vectors.
int16x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int16x4_t` vectors.
int16x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int16x4_t` vectors.
int16x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of eight packed `i16`.
int16x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int16x8_t` vectors.
int16x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int16x8_t` vectors.
int16x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int16x8_t` vectors.
int32x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of two packed `i32`.
int32x2x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int32x2_t` vectors.
int32x2x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int32x2_t` vectors.
int32x2x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int32x2_t` vectors.
int32x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of four packed `i32`.
int32x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int32x4_t` vectors.
int32x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int32x4_t` vectors.
int32x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int32x4_t` vectors.
int64x1_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of one packed `i64`.
int64x1x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int64x1_t` vectors.
int64x1x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int64x1_t` vectors.
int64x1x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int64x1_t` vectors.
int64x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of two packed `i64`.
int64x2x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `int64x2_t` vectors.
int64x2x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `int64x2_t` vectors.
int64x2x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `int64x2_t` vectors.
poly8x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide polynomial vector of eight packed `p8`.
poly8x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `poly8x8_t` vectors.
poly8x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `poly8x8_t` vectors.
poly8x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `poly8x8_t` vectors.
poly8x16_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of sixteen packed `p8`.
poly8x16x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `poly8x16_t` vectors.
poly8x16x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `poly8x16_t` vectors.
poly8x16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `poly8x16_t` vectors.
poly16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of four packed `p16`.
poly16x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `poly16x4_t` vectors.
poly16x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `poly16x4_t` vectors.
poly16x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `poly16x4_t` vectors.
poly16x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of eight packed `p16`.
poly16x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `poly16x8_t` vectors.
poly16x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `poly16x8_t` vectors.
poly16x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `poly16x8_t` vectors.
poly64x1_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of one packed `p64`.
poly64x1x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `poly64x1_t` vectors.
poly64x1x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `poly64x1_t` vectors.
poly64x1x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `poly64x1_t` vectors.
poly64x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of two packed `p64`.
poly64x2x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `poly64x2_t` vectors.
poly64x2x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `poly64x2_t` vectors.
poly64x2x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `poly64x2_t` vectors.
uint8x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of eight packed `u8`.
uint8x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint8x8_t` vectors.
uint8x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint8x8_t` vectors.
uint8x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint8x8_t` vectors.
uint8x16_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of sixteen packed `u8`.
uint8x16x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint8x16_t` vectors.
uint8x16x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint8x16_t` vectors.
uint8x16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint8x16_t` vectors.
uint16x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of four packed `u16`.
uint16x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint16x4_t` vectors.
uint16x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint16x4_t` vectors.
uint16x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint16x4_t` vectors.
uint16x8_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of eight packed `u16`.
uint16x8x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint16x8_t` vectors.
uint16x8x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint16x8_t` vectors.
uint16x8x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint16x8_t` vectors.
uint32x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of two packed `u32`.
uint32x2x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint32x2_t` vectors.
uint32x2x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint32x2_t` vectors.
uint32x2x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint32x2_t` vectors.
uint32x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of four packed `u32`.
uint32x4x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint32x4_t` vectors.
uint32x4x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint32x4_t` vectors.
uint32x4x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint32x4_t` vectors.
uint64x1_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 64-bit wide vector of one packed `u64`.
uint64x1x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint64x1_t` vectors.
uint64x1x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint64x1_t` vectors.
uint64x1x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint64x1_t` vectors.
uint64x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific 128-bit wide vector of two packed `u64`.
uint64x2x2_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing two `uint64x2_t` vectors.
uint64x2x3_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing three `uint64x2_t` vectors.
uint64x2x4_t(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Arm-specific type containing four `uint64x2_t` vectors.
SYExperimental(AArch64 or ARM or ARM64EC) and neither AArch64 nor ARM64EC nor `mclass` nor `v7`
  Full system is the required shareability domain, reads and writes are the required access types
svbool_tExperimental
  Scalable vector of type bool
svfloat32_tExperimental
  Scalable vector of type f32
svfloat32x2_tExperimental
  Two-element tuple of scalable vectors of type svfloat32_t
svfloat32x3_tExperimental
  Three-element tuple of scalable vectors of type svfloat32_t
svfloat32x4_tExperimental
  Four-element tuple of scalable vectors of type svfloat32_t
svfloat64_tExperimental
  Scalable vector of type f64
svfloat64x2_tExperimental
  Two-element tuple of scalable vectors of type svfloat64_t
svfloat64x3_tExperimental
  Three-element tuple of scalable vectors of type svfloat64_t
svfloat64x4_tExperimental
  Four-element tuple of scalable vectors of type svfloat64_t
svint8_tExperimental
  Scalable vector of type i8
svint8x2_tExperimental
  Two-element tuple of scalable vectors of type svint8_t
svint8x3_tExperimental
  Three-element tuple of scalable vectors of type svint8_t
svint8x4_tExperimental
  Four-element tuple of scalable vectors of type svint8_t
svint16_tExperimental
  Scalable vector of type i16
svint16x2_tExperimental
  Two-element tuple of scalable vectors of type svint16_t
svint16x3_tExperimental
  Three-element tuple of scalable vectors of type svint16_t
svint16x4_tExperimental
  Four-element tuple of scalable vectors of type svint16_t
svint32_tExperimental
  Scalable vector of type i32
svint32x2_tExperimental
  Two-element tuple of scalable vectors of type svint32_t
svint32x3_tExperimental
  Three-element tuple of scalable vectors of type svint32_t
svint32x4_tExperimental
  Four-element tuple of scalable vectors of type svint32_t
svint64_tExperimental
  Scalable vector of type i64
svint64x2_tExperimental
  Two-element tuple of scalable vectors of type svint64_t
svint64x3_tExperimental
  Three-element tuple of scalable vectors of type svint64_t
svint64x4_tExperimental
  Four-element tuple of scalable vectors of type svint64_t
svuint8_tExperimental
  Scalable vector of type u8
svuint8x2_tExperimental
  Two-element tuple of scalable vectors of type svuint8_t
svuint8x3_tExperimental
  Three-element tuple of scalable vectors of type svuint8_t
svuint8x4_tExperimental
  Four-element tuple of scalable vectors of type svuint8_t
svuint16_tExperimental
  Scalable vector of type u16
svuint16x2_tExperimental
  Two-element tuple of scalable vectors of type svuint16_t
svuint16x3_tExperimental
  Three-element tuple of scalable vectors of type svuint16_t
svuint16x4_tExperimental
  Four-element tuple of scalable vectors of type svuint16_t
svuint32_tExperimental
  Scalable vector of type u32
svuint32x2_tExperimental
  Two-element tuple of scalable vectors of type svuint32_t
svuint32x3_tExperimental
  Three-element tuple of scalable vectors of type svuint32_t
svuint32x4_tExperimental
  Four-element tuple of scalable vectors of type svuint32_t
svuint64_tExperimental
  Scalable vector of type u64
svuint64x2_tExperimental
  Two-element tuple of scalable vectors of type svuint64_t
svuint64x3_tExperimental
  Three-element tuple of scalable vectors of type svuint64_t
svuint64x4_tExperimental
  Four-element tuple of scalable vectors of type svuint64_t

## Enums§

svpatternExperimental
  Patterns returned by a `PTRUE`
svprfopExperimental
  Addressing mode for prefetch intrinsics - allows the specification of the expected access kind (read or write), the cache level to load the data, the data retention policy (temporal or streaming)

## Constants§

_PREFETCH_LOCALITY0Experimental
  See `prefetch`.
_PREFETCH_LOCALITY1Experimental
  See `prefetch`.
_PREFETCH_LOCALITY2Experimental
  See `prefetch`.
_PREFETCH_LOCALITY3Experimental
  See `prefetch`.
_PREFETCH_READExperimental
  See `prefetch`.
_PREFETCH_WRITEExperimental
  See `prefetch`.

## Functions§

__crc32b`crc` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  CRC32 single round checksum for bytes (8 bits). Arm’s documentation
__crc32cb`crc` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  CRC32-C single round checksum for bytes (8 bits). Arm’s documentation
__crc32cd`crc`
  CRC32-C single round checksum for quad words (64 bits). Arm’s documentation
__crc32ch`crc` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  CRC32-C single round checksum for bytes (16 bits). Arm’s documentation
__crc32cw`crc` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  CRC32-C single round checksum for bytes (32 bits). Arm’s documentation
__crc32d`crc`
  CRC32 single round checksum for quad words (64 bits). Arm’s documentation
__crc32h`crc` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  CRC32 single round checksum for bytes (16 bits). Arm’s documentation
__crc32w`crc` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  CRC32 single round checksum for bytes (32 bits). Arm’s documentation
__jcvt`jsconv`
  Floating-point JavaScript convert to signed fixed-point, rounding toward zero Arm’s documentation
vaba_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (64-bit) Arm’s documentation
vaba_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (64-bit) Arm’s documentation
vaba_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (64-bit) Arm’s documentation
vaba_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (64-bit) Arm’s documentation
vaba_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (64-bit) Arm’s documentation
vaba_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (64-bit) Arm’s documentation
vabal_high_s8`neon`
  Signed Absolute difference and Accumulate Long Arm’s documentation
vabal_high_s16`neon`
  Signed Absolute difference and Accumulate Long Arm’s documentation
vabal_high_s32`neon`
  Signed Absolute difference and Accumulate Long Arm’s documentation
vabal_high_u8`neon`
  Unsigned Absolute difference and Accumulate Long Arm’s documentation
vabal_high_u16`neon`
  Unsigned Absolute difference and Accumulate Long Arm’s documentation
vabal_high_u32`neon`
  Unsigned Absolute difference and Accumulate Long Arm’s documentation
vabal_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Absolute difference and Accumulate Long Arm’s documentation
vabal_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Absolute difference and Accumulate Long Arm’s documentation
vabal_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Absolute difference and Accumulate Long Arm’s documentation
vabal_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Absolute difference and Accumulate Long Arm’s documentation
vabal_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Absolute difference and Accumulate Long Arm’s documentation
vabal_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Absolute difference and Accumulate Long Arm’s documentation
vabaq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (128-bit) Arm’s documentation
vabaq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (128-bit) Arm’s documentation
vabaq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (128-bit) Arm’s documentation
vabaq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (128-bit) Arm’s documentation
vabaq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (128-bit) Arm’s documentation
vabaq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference and accumulate (128-bit) Arm’s documentation
vabd_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Absolute difference between the arguments of Floating Arm’s documentation
vabd_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments of Floating Arm’s documentation
vabd_f64`neon`
  Absolute difference between the arguments of Floating Arm’s documentation
vabd_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabd_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabd_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabd_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabd_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabd_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabdd_f64`neon`
  Floating-point absolute difference Arm’s documentation
vabdl_high_s8`neon`
  Signed Absolute difference Long Arm’s documentation
vabdl_high_s16`neon`
  Signed Absolute difference Long Arm’s documentation
vabdl_high_s32`neon`
  Signed Absolute difference Long Arm’s documentation
vabdl_high_u8`neon`
  Unsigned Absolute difference Long Arm’s documentation
vabdl_high_u16`neon`
  Unsigned Absolute difference Long Arm’s documentation
vabdl_high_u32`neon`
  Unsigned Absolute difference Long Arm’s documentation
vabdl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Absolute difference Long Arm’s documentation
vabdl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Absolute difference Long Arm’s documentation
vabdl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Absolute difference Long Arm’s documentation
vabdl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Absolute difference Long Arm’s documentation
vabdl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Absolute difference Long Arm’s documentation
vabdl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Absolute difference Long Arm’s documentation
vabdq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Absolute difference between the arguments of Floating Arm’s documentation
vabdq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments of Floating Arm’s documentation
vabdq_f64`neon`
  Absolute difference between the arguments of Floating Arm’s documentation
vabdq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabdq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabdq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabdq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabdq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabdq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute difference between the arguments Arm’s documentation
vabds_f32`neon`
  Floating-point absolute difference Arm’s documentation
vabs_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute value Arm’s documentation
vabs_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute value Arm’s documentation
vabs_f64`neon`
  Floating-point absolute value Arm’s documentation
vabs_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute value (wrapping). Arm’s documentation
vabs_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute value (wrapping). Arm’s documentation
vabs_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute value (wrapping). Arm’s documentation
vabs_s64`neon`
  Absolute Value (wrapping). Arm’s documentation
vabsd_s64`neon`
  Absolute Value (wrapping). Arm’s documentation
vabsq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute value Arm’s documentation
vabsq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute value Arm’s documentation
vabsq_f64`neon`
  Floating-point absolute value Arm’s documentation
vabsq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute value (wrapping). Arm’s documentation
vabsq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute value (wrapping). Arm’s documentation
vabsq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Absolute value (wrapping). Arm’s documentation
vabsq_s64`neon`
  Absolute Value (wrapping). Arm’s documentation
vadd_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point Add (vector). Arm’s documentation
vadd_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_f64`neon`
  Vector add.
vadd_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vadd_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vadd_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vadd_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_s64`neon`
  Vector add.
vadd_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vadd_u64`neon`
  Vector add.
vaddd_s64`neon`
  Vector add.
vaddd_u64`neon`
  Vector add.
vaddhn_high_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow (high half). Arm’s documentation
vaddhn_high_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow (high half). Arm’s documentation
vaddhn_high_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow (high half). Arm’s documentation
vaddhn_high_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow (high half). Arm’s documentation
vaddhn_high_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow (high half). Arm’s documentation
vaddhn_high_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow (high half). Arm’s documentation
vaddhn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow. Arm’s documentation
vaddhn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow. Arm’s documentation
vaddhn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow. Arm’s documentation
vaddhn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow. Arm’s documentation
vaddhn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow. Arm’s documentation
vaddhn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add returning High Narrow. Arm’s documentation
vaddl_high_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add Long (vector, high half). Arm’s documentation
vaddl_high_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add Long (vector, high half). Arm’s documentation
vaddl_high_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add Long (vector, high half). Arm’s documentation
vaddl_high_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add Long (vector, high half). Arm’s documentation
vaddl_high_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add Long (vector, high half). Arm’s documentation
vaddl_high_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add Long (vector, high half). Arm’s documentation
vaddl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Long (vector). Arm’s documentation
vaddl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Long (vector). Arm’s documentation
vaddl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Long (vector). Arm’s documentation
vaddl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Long (vector). Arm’s documentation
vaddl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Long (vector). Arm’s documentation
vaddl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Long (vector). Arm’s documentation
vaddlv_s8`neon`
  Signed Add Long across Vector Arm’s documentation
vaddlv_s16`neon`
  Signed Add Long across Vector Arm’s documentation
vaddlv_s32`neon`
  Signed Add Long across Vector Arm’s documentation
vaddlv_u8`neon`
  Unsigned Add Long across Vector Arm’s documentation
vaddlv_u16`neon`
  Unsigned Add Long across Vector Arm’s documentation
vaddlv_u32`neon`
  Unsigned Add Long across Vector Arm’s documentation
vaddlvq_s8`neon`
  Signed Add Long across Vector Arm’s documentation
vaddlvq_s16`neon`
  Signed Add Long across Vector Arm’s documentation
vaddlvq_s32`neon`
  Signed Add Long across Vector Arm’s documentation
vaddlvq_u8`neon`
  Unsigned Add Long across Vector Arm’s documentation
vaddlvq_u16`neon`
  Unsigned Add Long across Vector Arm’s documentation
vaddlvq_u32`neon`
  Unsigned Add Long across Vector Arm’s documentation
vaddq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point Add (vector). Arm’s documentation
vaddq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_f64`neon`
  Vector add.
vaddq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vaddq_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vaddq_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vaddq_p128`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise exclusive OR Arm’s documentation
vaddq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector add. Arm’s documentation
vaddv_f32`neon`
  Floating-point add across vector Arm’s documentation
vaddv_s8`neon`
  Add across vector Arm’s documentation
vaddv_s16`neon`
  Add across vector Arm’s documentation
vaddv_s32`neon`
  Add across vector Arm’s documentation
vaddv_u8`neon`
  Add across vector Arm’s documentation
vaddv_u16`neon`
  Add across vector Arm’s documentation
vaddv_u32`neon`
  Add across vector Arm’s documentation
vaddvq_f32`neon`
  Floating-point add across vector Arm’s documentation
vaddvq_f64`neon`
  Floating-point add across vector Arm’s documentation
vaddvq_s8`neon`
  Add across vector Arm’s documentation
vaddvq_s16`neon`
  Add across vector Arm’s documentation
vaddvq_s32`neon`
  Add across vector Arm’s documentation
vaddvq_s64`neon`
  Add across vector Arm’s documentation
vaddvq_u8`neon`
  Add across vector Arm’s documentation
vaddvq_u16`neon`
  Add across vector Arm’s documentation
vaddvq_u32`neon`
  Add across vector Arm’s documentation
vaddvq_u64`neon`
  Add across vector Arm’s documentation
vaddw_high_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide (high half). Arm’s documentation
vaddw_high_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide (high half). Arm’s documentation
vaddw_high_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide (high half). Arm’s documentation
vaddw_high_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide (high half). Arm’s documentation
vaddw_high_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide (high half). Arm’s documentation
vaddw_high_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide (high half). Arm’s documentation
vaddw_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide Arm’s documentation
vaddw_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide Arm’s documentation
vaddw_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide Arm’s documentation
vaddw_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide Arm’s documentation
vaddw_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide Arm’s documentation
vaddw_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add Wide Arm’s documentation
vaesdq_u8Little-endian and `aes` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  AES single round encryption. Arm’s documentation
vaeseq_u8Little-endian and `aes` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  AES single round encryption. Arm’s documentation
vaesimcq_u8Little-endian and `aes` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  AES inverse mix columns. Arm’s documentation
vaesmcq_u8Little-endian and `aes` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  AES mix columns. Arm’s documentation
vand_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vand_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vandq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise and Arm’s documentation
vbcaxq_s8`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_s16`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_s32`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_s64`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_u8`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_u16`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_u32`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbcaxq_u64`neon` and `sha3`
  Bit clear and exclusive OR Arm’s documentation
vbic_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbic_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbicq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise bit clear. Arm’s documentation
vbsl_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Bitwise Select. Arm’s documentation
vbsl_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_f64`neon`
  Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.
vbsl_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_p64`neon`
  Bitwise Select.
vbsl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbsl_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Bitwise Select. Arm’s documentation
vbslq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_f64`neon`
  Bitwise Select. (128-bit)
vbslq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_p64`neon`
  Bitwise Select. (128-bit)
vbslq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vbslq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Bitwise Select. Arm’s documentation
vcage_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare greater than or equal Arm’s documentation
vcage_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare greater than or equal Arm’s documentation
vcage_f64`neon`
  Floating-point absolute compare greater than or equal Arm’s documentation
vcaged_f64`neon`
  Floating-point absolute compare greater than or equal Arm’s documentation
vcageq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare greater than or equal Arm’s documentation
vcageq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare greater than or equal Arm’s documentation
vcageq_f64`neon`
  Floating-point absolute compare greater than or equal Arm’s documentation
vcages_f32`neon`
  Floating-point absolute compare greater than or equal Arm’s documentation
vcagt_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare greater than Arm’s documentation
vcagt_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare greater than Arm’s documentation
vcagt_f64`neon`
  Floating-point absolute compare greater than Arm’s documentation
vcagtd_f64`neon`
  Floating-point absolute compare greater than Arm’s documentation
vcagtq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare greater than Arm’s documentation
vcagtq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare greater than Arm’s documentation
vcagtq_f64`neon`
  Floating-point absolute compare greater than Arm’s documentation
vcagts_f32`neon`
  Floating-point absolute compare greater than Arm’s documentation
vcale_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare less than or equal Arm’s documentation
vcale_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare less than or equal Arm’s documentation
vcale_f64`neon`
  Floating-point absolute compare less than or equal Arm’s documentation
vcaled_f64`neon`
  Floating-point absolute compare less than or equal Arm’s documentation
vcaleq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare less than or equal Arm’s documentation
vcaleq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare less than or equal Arm’s documentation
vcaleq_f64`neon`
  Floating-point absolute compare less than or equal Arm’s documentation
vcales_f32`neon`
  Floating-point absolute compare less than or equal Arm’s documentation
vcalt_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare less than Arm’s documentation
vcalt_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare less than Arm’s documentation
vcalt_f64`neon`
  Floating-point absolute compare less than Arm’s documentation
vcaltd_f64`neon`
  Floating-point absolute compare less than Arm’s documentation
vcaltq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute compare less than Arm’s documentation
vcaltq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point absolute compare less than Arm’s documentation
vcaltq_f64`neon`
  Floating-point absolute compare less than Arm’s documentation
vcalts_f32`neon`
  Floating-point absolute compare less than Arm’s documentation
vceq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare equal Arm’s documentation
vceq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare equal Arm’s documentation
vceq_f64`neon`
  Floating-point compare equal Arm’s documentation
vceq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_p64`neon`
  Compare bitwise Equal (vector) Arm’s documentation
vceq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_s64`neon`
  Compare bitwise Equal (vector) Arm’s documentation
vceq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceq_u64`neon`
  Compare bitwise Equal (vector) Arm’s documentation
vceqd_f64`neon`
  Floating-point compare equal Arm’s documentation
vceqd_s64`neon`
  Compare bitwise equal Arm’s documentation
vceqd_u64`neon`
  Compare bitwise equal Arm’s documentation
vceqq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare equal Arm’s documentation
vceqq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare equal Arm’s documentation
vceqq_f64`neon`
  Floating-point compare equal Arm’s documentation
vceqq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_p64`neon`
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_s64`neon`
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare bitwise Equal (vector) Arm’s documentation
vceqq_u64`neon`
  Compare bitwise Equal (vector) Arm’s documentation
vceqs_f32`neon`
  Floating-point compare equal Arm’s documentation
vceqz_f16`fp16` and `neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqz_f32`neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqz_f64`neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqz_p8`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqz_p64`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqz_s8`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqz_s16`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqz_s32`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqz_s64`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqz_u8`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqz_u16`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqz_u32`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqz_u64`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqzd_f64`neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqzd_s64`neon`
  Compare bitwise equal to zero Arm’s documentation
vceqzd_u64`neon`
  Compare bitwise equal to zero Arm’s documentation
vceqzq_f16`fp16` and `neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqzq_f32`neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqzq_f64`neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vceqzq_p8`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqzq_p64`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqzq_s8`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqzq_s16`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqzq_s32`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqzq_s64`neon`
  Signed compare bitwise equal to zero Arm’s documentation
vceqzq_u8`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqzq_u16`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqzq_u32`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqzq_u64`neon`
  Unsigned compare bitwise equal to zero Arm’s documentation
vceqzs_f32`neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vcge_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than or equal Arm’s documentation
vcge_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare greater than or equal Arm’s documentation
vcge_f64`neon`
  Floating-point compare greater than or equal Arm’s documentation
vcge_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than or equal Arm’s documentation
vcge_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than or equal Arm’s documentation
vcge_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than or equal Arm’s documentation
vcge_s64`neon`
  Compare signed greater than or equal Arm’s documentation
vcge_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than or equal Arm’s documentation
vcge_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than or equal Arm’s documentation
vcge_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than or equal Arm’s documentation
vcge_u64`neon`
  Compare unsigned greater than or equal Arm’s documentation
vcged_f64`neon`
  Floating-point compare greater than or equal Arm’s documentation
vcged_s64`neon`
  Compare greater than or equal Arm’s documentation
vcged_u64`neon`
  Compare greater than or equal Arm’s documentation
vcgeq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than or equal Arm’s documentation
vcgeq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare greater than or equal Arm’s documentation
vcgeq_f64`neon`
  Floating-point compare greater than or equal Arm’s documentation
vcgeq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than or equal Arm’s documentation
vcgeq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than or equal Arm’s documentation
vcgeq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than or equal Arm’s documentation
vcgeq_s64`neon`
  Compare signed greater than or equal Arm’s documentation
vcgeq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than or equal Arm’s documentation
vcgeq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than or equal Arm’s documentation
vcgeq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than or equal Arm’s documentation
vcgeq_u64`neon`
  Compare unsigned greater than or equal Arm’s documentation
vcges_f32`neon`
  Floating-point compare greater than or equal Arm’s documentation
vcgez_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgez_f32`neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgez_f64`neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgez_s8`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgez_s16`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgez_s32`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgez_s64`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgezd_f64`neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgezd_s64`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgezq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgezq_f32`neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgezq_f64`neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgezq_s8`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgezq_s16`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgezq_s32`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgezq_s64`neon`
  Compare signed greater than or equal to zero Arm’s documentation
vcgezs_f32`neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgt_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than Arm’s documentation
vcgt_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare greater than Arm’s documentation
vcgt_f64`neon`
  Floating-point compare greater than Arm’s documentation
vcgt_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than Arm’s documentation
vcgt_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than Arm’s documentation
vcgt_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than Arm’s documentation
vcgt_s64`neon`
  Compare signed greater than Arm’s documentation
vcgt_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than Arm’s documentation
vcgt_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than Arm’s documentation
vcgt_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than Arm’s documentation
vcgt_u64`neon`
  Compare unsigned greater than Arm’s documentation
vcgtd_f64`neon`
  Floating-point compare greater than Arm’s documentation
vcgtd_s64`neon`
  Compare greater than Arm’s documentation
vcgtd_u64`neon`
  Compare greater than Arm’s documentation
vcgtq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than Arm’s documentation
vcgtq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare greater than Arm’s documentation
vcgtq_f64`neon`
  Floating-point compare greater than Arm’s documentation
vcgtq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than Arm’s documentation
vcgtq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than Arm’s documentation
vcgtq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed greater than Arm’s documentation
vcgtq_s64`neon`
  Compare signed greater than Arm’s documentation
vcgtq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than Arm’s documentation
vcgtq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than Arm’s documentation
vcgtq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned greater than Arm’s documentation
vcgtq_u64`neon`
  Compare unsigned greater than Arm’s documentation
vcgts_f32`neon`
  Floating-point compare greater than Arm’s documentation
vcgtz_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than zero Arm’s documentation
vcgtz_f32`neon`
  Floating-point compare greater than zero Arm’s documentation
vcgtz_f64`neon`
  Floating-point compare greater than zero Arm’s documentation
vcgtz_s8`neon`
  Compare signed greater than zero Arm’s documentation
vcgtz_s16`neon`
  Compare signed greater than zero Arm’s documentation
vcgtz_s32`neon`
  Compare signed greater than zero Arm’s documentation
vcgtz_s64`neon`
  Compare signed greater than zero Arm’s documentation
vcgtzd_f64`neon`
  Floating-point compare greater than zero Arm’s documentation
vcgtzd_s64`neon`
  Compare signed greater than zero Arm’s documentation
vcgtzq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare greater than zero Arm’s documentation
vcgtzq_f32`neon`
  Floating-point compare greater than zero Arm’s documentation
vcgtzq_f64`neon`
  Floating-point compare greater than zero Arm’s documentation
vcgtzq_s8`neon`
  Compare signed greater than zero Arm’s documentation
vcgtzq_s16`neon`
  Compare signed greater than zero Arm’s documentation
vcgtzq_s32`neon`
  Compare signed greater than zero Arm’s documentation
vcgtzq_s64`neon`
  Compare signed greater than zero Arm’s documentation
vcgtzs_f32`neon`
  Floating-point compare greater than zero Arm’s documentation
vcle_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than or equal Arm’s documentation
vcle_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare less than or equal Arm’s documentation
vcle_f64`neon`
  Floating-point compare less than or equal Arm’s documentation
vcle_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than or equal Arm’s documentation
vcle_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than or equal Arm’s documentation
vcle_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than or equal Arm’s documentation
vcle_s64`neon`
  Compare signed less than or equal Arm’s documentation
vcle_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than or equal Arm’s documentation
vcle_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than or equal Arm’s documentation
vcle_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than or equal Arm’s documentation
vcle_u64`neon`
  Compare unsigned less than or equal Arm’s documentation
vcled_f64`neon`
  Floating-point compare less than or equal Arm’s documentation
vcled_s64`neon`
  Compare less than or equal Arm’s documentation
vcled_u64`neon`
  Compare less than or equal Arm’s documentation
vcleq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than or equal Arm’s documentation
vcleq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare less than or equal Arm’s documentation
vcleq_f64`neon`
  Floating-point compare less than or equal Arm’s documentation
vcleq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than or equal Arm’s documentation
vcleq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than or equal Arm’s documentation
vcleq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than or equal Arm’s documentation
vcleq_s64`neon`
  Compare signed less than or equal Arm’s documentation
vcleq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than or equal Arm’s documentation
vcleq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than or equal Arm’s documentation
vcleq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than or equal Arm’s documentation
vcleq_u64`neon`
  Compare unsigned less than or equal Arm’s documentation
vcles_f32`neon`
  Floating-point compare less than or equal Arm’s documentation
vclez_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than or equal to zero Arm’s documentation
vclez_f32`neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vclez_f64`neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vclez_s8`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclez_s16`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclez_s32`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclez_s64`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclezd_f64`neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vclezd_s64`neon`
  Compare less than or equal to zero Arm’s documentation
vclezq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than or equal to zero Arm’s documentation
vclezq_f32`neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vclezq_f64`neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vclezq_s8`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclezq_s16`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclezq_s32`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclezq_s64`neon`
  Compare signed less than or equal to zero Arm’s documentation
vclezs_f32`neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vcls_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vcls_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vcls_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vcls_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vcls_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vcls_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclsq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclsq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclsq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclsq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclsq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclsq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading sign bits Arm’s documentation
vclt_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than Arm’s documentation
vclt_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare less than Arm’s documentation
vclt_f64`neon`
  Floating-point compare less than Arm’s documentation
vclt_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than Arm’s documentation
vclt_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than Arm’s documentation
vclt_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than Arm’s documentation
vclt_s64`neon`
  Compare signed less than Arm’s documentation
vclt_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than Arm’s documentation
vclt_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than Arm’s documentation
vclt_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than Arm’s documentation
vclt_u64`neon`
  Compare unsigned less than Arm’s documentation
vcltd_f64`neon`
  Floating-point compare less than Arm’s documentation
vcltd_s64`neon`
  Compare less than Arm’s documentation
vcltd_u64`neon`
  Compare less than Arm’s documentation
vcltq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than Arm’s documentation
vcltq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point compare less than Arm’s documentation
vcltq_f64`neon`
  Floating-point compare less than Arm’s documentation
vcltq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than Arm’s documentation
vcltq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than Arm’s documentation
vcltq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare signed less than Arm’s documentation
vcltq_s64`neon`
  Compare signed less than Arm’s documentation
vcltq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than Arm’s documentation
vcltq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than Arm’s documentation
vcltq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Compare unsigned less than Arm’s documentation
vcltq_u64`neon`
  Compare unsigned less than Arm’s documentation
vclts_f32`neon`
  Floating-point compare less than Arm’s documentation
vcltz_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than Arm’s documentation
vcltz_f32`neon`
  Floating-point compare less than zero Arm’s documentation
vcltz_f64`neon`
  Floating-point compare less than zero Arm’s documentation
vcltz_s8`neon`
  Compare signed less than zero Arm’s documentation
vcltz_s16`neon`
  Compare signed less than zero Arm’s documentation
vcltz_s32`neon`
  Compare signed less than zero Arm’s documentation
vcltz_s64`neon`
  Compare signed less than zero Arm’s documentation
vcltzd_f64`neon`
  Floating-point compare less than zero Arm’s documentation
vcltzd_s64`neon`
  Compare less than zero Arm’s documentation
vcltzq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point compare less than Arm’s documentation
vcltzq_f32`neon`
  Floating-point compare less than zero Arm’s documentation
vcltzq_f64`neon`
  Floating-point compare less than zero Arm’s documentation
vcltzq_s8`neon`
  Compare signed less than zero Arm’s documentation
vcltzq_s16`neon`
  Compare signed less than zero Arm’s documentation
vcltzq_s32`neon`
  Compare signed less than zero Arm’s documentation
vcltzq_s64`neon`
  Compare signed less than zero Arm’s documentation
vcltzs_f32`neon`
  Floating-point compare less than zero Arm’s documentation
vclz_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclz_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclz_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclz_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclz_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclz_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclzq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclzq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclzq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclzq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclzq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vclzq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Count leading zero bits Arm’s documentation
vcnt_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Population count per byte. Arm’s documentation
vcnt_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Population count per byte. Arm’s documentation
vcnt_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Population count per byte. Arm’s documentation
vcntq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Population count per byte. Arm’s documentation
vcntq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Population count per byte. Arm’s documentation
vcntq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Population count per byte. Arm’s documentation
vcombine_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_f64`neon`
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_p64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcombine_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Join two smaller vectors into a single larger vector Arm’s documentation
vcopy_lane_f32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_p8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_p16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_p64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_s8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_s16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_s32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_s64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_u8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_u16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_u32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_lane_u64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_f32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_p8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_p16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_p64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_s8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_s16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_s32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_s64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_u8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_u16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_u32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopy_laneq_u64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_f32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_p8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_p16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_p64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_s8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_s16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_s32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_s64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_u8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_u16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_u32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_lane_u64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_f32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_p8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_p16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_p64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_s8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_s16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_s32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_s64`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_u8`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_u16`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_u32`neon`
  Insert vector element from another vector element Arm’s documentation
vcopyq_laneq_u64`neon`
  Insert vector element from another vector element Arm’s documentation
vcreate_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Insert vector element from another vector element Arm’s documentation
vcreate_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vcreate_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_p64`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcreate_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vcvt_f16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to lower precision narrow Arm’s documentation
vcvt_f16_s16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvt_f16_u16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvt_f32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to higher precision long Arm’s documentation
vcvt_f32_f64`neon`
  Floating-point convert Arm’s documentation
vcvt_f32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Fixed-point convert to floating-point Arm’s documentation
vcvt_f32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Fixed-point convert to floating-point Arm’s documentation
vcvt_f64_f32`neon`
  Floating-point convert to higher precision long Arm’s documentation
vcvt_f64_s64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvt_f64_u64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvt_high_f16_f32`neon`
  Floating-point convert to lower precision Arm’s documentation
vcvt_high_f32_f16`neon`
  Floating-point convert to higher precision Arm’s documentation
vcvt_high_f32_f64`neon`
  Floating-point convert to lower precision narrow Arm’s documentation
vcvt_high_f64_f32`neon`
  Floating-point convert to higher precision long Arm’s documentation
vcvt_n_f16_s16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvt_n_f16_u16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvt_n_f32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Fixed-point convert to floating-point Arm’s documentation
vcvt_n_f32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Fixed-point convert to floating-point Arm’s documentation
vcvt_n_f64_s64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvt_n_f64_u64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvt_n_s16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to signed fixed-point Arm’s documentation
vcvt_n_s32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvt_n_s64_f64`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvt_n_u16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvt_n_u32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvt_n_u64_f64`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvt_s16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation
vcvt_s32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation
vcvt_s64_f64`neon`
  Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation
vcvt_u16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvt_u32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvt_u64_f64`neon`
  Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvta_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation
vcvta_s32_f32`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation
vcvta_s64_f64`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation
vcvta_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation
vcvta_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation
vcvta_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation
vcvtad_s64_f64`neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtad_u64_f64`neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtaq_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation
vcvtaq_s32_f32`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation
vcvtaq_s64_f64`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to away Arm’s documentation
vcvtaq_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation
vcvtaq_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation
vcvtaq_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to away Arm’s documentation
vcvtas_s32_f32`neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtas_u32_f32`neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtd_f64_s64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtd_f64_u64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtd_n_f64_s64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtd_n_f64_u64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtd_n_s64_f64`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvtd_n_u64_f64`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvtd_s64_f64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtd_u64_f64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtm_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtm_s32_f32`neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtm_s64_f64`neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtm_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtm_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtm_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtmd_s64_f64`neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtmd_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtmq_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtmq_s32_f32`neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtmq_s64_f64`neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtmq_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtmq_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtmq_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtms_s32_f32`neon`
  Floating-point convert to signed integer, rounding toward minus infinity Arm’s documentation
vcvtms_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding toward minus infinity Arm’s documentation
vcvtn_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtn_s32_f32`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtn_s64_f64`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtn_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtn_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtn_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtnd_s64_f64`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtnd_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtnq_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtnq_s32_f32`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtnq_s64_f64`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtnq_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtnq_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtnq_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtns_s32_f32`neon`
  Floating-point convert to signed integer, rounding to nearest with ties to even Arm’s documentation
vcvtns_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtp_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding to plus infinity Arm’s documentation
vcvtp_s32_f32`neon`
  Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation
vcvtp_s64_f64`neon`
  Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation
vcvtp_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation
vcvtp_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation
vcvtp_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation
vcvtpd_s64_f64`neon`
  Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation
vcvtpd_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation
vcvtpq_s16_f16`fp16` and `neon`
  Floating-point convert to signed integer, rounding to plus infinity Arm’s documentation
vcvtpq_s32_f32`neon`
  Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation
vcvtpq_s64_f64`neon`
  Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation
vcvtpq_u16_f16`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation
vcvtpq_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation
vcvtpq_u64_f64`neon`
  Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation
vcvtps_s32_f32`neon`
  Floating-point convert to signed integer, rounding toward plus infinity Arm’s documentation
vcvtps_u32_f32`neon`
  Floating-point convert to unsigned integer, rounding toward plus infinity Arm’s documentation
vcvtq_f16_s16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_f16_u16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_f32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_f32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_f64_s64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_f64_u64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_f16_s16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_f16_u16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_f32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_f32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_f64_s64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_f64_u64`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtq_n_s16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to signed fixed-point Arm’s documentation
vcvtq_n_s32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvtq_n_s64_f64`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvtq_n_u16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Fixed-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvtq_n_u32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvtq_n_u64_f64`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvtq_s16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation
vcvtq_s32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation
vcvtq_s64_f64`neon`
  Floating-point convert to signed fixed-point, rounding toward zero Arm’s documentation
vcvtq_u16_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvtq_u32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvtq_u64_f64`neon`
  Floating-point convert to unsigned fixed-point, rounding toward zero Arm’s documentation
vcvts_f32_s32`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvts_f32_u32`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvts_n_f32_s32`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvts_n_f32_u32`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvts_n_s32_f32`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvts_n_u32_f32`neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvts_s32_f32`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvts_u32_f32`neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvtx_f32_f64`neon`
  Floating-point convert to lower precision narrow, rounding to odd Arm’s documentation
vcvtx_high_f32_f64`neon`
  Floating-point convert to lower precision narrow, rounding to odd Arm’s documentation
vcvtxd_f32_f64`neon`
  Floating-point convert to lower precision narrow, rounding to odd Arm’s documentation
vdiv_f16`fp16` and `neon`
  Divide Arm’s documentation
vdiv_f32`neon`
  Divide Arm’s documentation
vdiv_f64`neon`
  Divide Arm’s documentation
vdivq_f16`fp16` and `neon`
  Divide Arm’s documentation
vdivq_f32`neon`
  Divide Arm’s documentation
vdivq_f64`neon`
  Divide Arm’s documentation
vdot_lane_s32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdot_lane_u32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdot_laneq_s32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdot_laneq_u32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdot_s32Little-endian and `dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (vector) Arm’s documentation
vdot_u32Little-endian and `dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (vector) Arm’s documentation
vdotq_lane_s32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdotq_lane_u32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdotq_laneq_s32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdotq_laneq_u32`dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (indexed) Arm’s documentation
vdotq_s32Little-endian and `dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (vector) Arm’s documentation
vdotq_u32Little-endian and `dotprod` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product arithmetic (vector) Arm’s documentation
vdup_lane_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_f64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_p64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_lane_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_f64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_p64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_laneq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdup_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_f64`neon`
  Duplicate vector element to vector or scalar
vdup_n_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_p64`neon`
  Duplicate vector element to vector or scalar
vdup_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdup_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupb_lane_p8`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupb_lane_s8`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupb_lane_u8`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupb_laneq_p8`neon`
  Extract an element from a vector Arm’s documentation
vdupb_laneq_s8`neon`
  Extract an element from a vector Arm’s documentation
vdupb_laneq_u8`neon`
  Extract an element from a vector Arm’s documentation
vdupd_lane_f64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupd_lane_s64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupd_lane_u64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupd_laneq_f64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupd_laneq_s64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupd_laneq_u64`neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_lane_p16`neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_lane_s16`neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_lane_u16`neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_laneq_p16`neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_laneq_s16`neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_laneq_u16`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_f64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_p64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_lane_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_f64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_p64`neon`
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_laneq_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Set all vector lanes to the same value Arm’s documentation
vdupq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_f64`neon`
  Duplicate vector element to vector or scalar
vdupq_n_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_p64`neon`
  Duplicate vector element to vector or scalar
vdupq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdupq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vdups_lane_f32`neon`
  Set all vector lanes to the same value Arm’s documentation
vdups_lane_s32`neon`
  Set all vector lanes to the same value Arm’s documentation
vdups_lane_u32`neon`
  Set all vector lanes to the same value Arm’s documentation
vdups_laneq_f32`neon`
  Set all vector lanes to the same value Arm’s documentation
vdups_laneq_s32`neon`
  Set all vector lanes to the same value Arm’s documentation
vdups_laneq_u32`neon`
  Set all vector lanes to the same value Arm’s documentation
veor3q_s8`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_s16`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_s32`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_s64`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_u8`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_u16`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_u32`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor3q_u64`neon` and `sha3`
  Three-way exclusive OR Arm’s documentation
veor_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veor_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
veorq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise exclusive or (vector) Arm’s documentation
vext_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Extract vector from pair of vectors Arm’s documentation
vext_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_f64`neon`
  Extract vector from pair of vectors
vext_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_p64`neon`
  Extract vector from pair of vectors
vext_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vext_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Extract vector from pair of vectors Arm’s documentation
vextq_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_f64`neon`
  Extract vector from pair of vectors Arm’s documentation
vextq_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_p64`neon`
  Extract vector from pair of vectors Arm’s documentation
vextq_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vextq_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Extract vector from pair of vectors Arm’s documentation
vfma_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point fused Multiply-Add to accumulator (vector) Arm’s documentation
vfma_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfma_f64`neon`
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfma_lane_f16`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfma_lane_f32`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfma_lane_f64`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfma_laneq_f16`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfma_laneq_f32`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfma_laneq_f64`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfma_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfma_n_f64`neon`
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfmad_lane_f64`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmad_laneq_f64`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point fused Multiply-Add to accumulator (vector) Arm’s documentation
vfmaq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfmaq_f64`neon`
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfmaq_lane_f16`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_lane_f32`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_lane_f64`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_laneq_f16`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_laneq_f32`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_laneq_f64`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfmaq_n_f64`neon`
  Floating-point fused Multiply-Add to accumulator(vector) Arm’s documentation
vfmas_lane_f32`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmas_laneq_f32`neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmlal_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation
vfmlal_lane_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlal_lane_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlal_laneq_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlal_laneq_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlal_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation
vfmlalq_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation
vfmlalq_lane_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlalq_lane_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlalq_laneq_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlalq_laneq_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (by element). Arm’s documentation
vfmlalq_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Add Long to accumulator (vector). Arm’s documentation
vfmlsl_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation
vfmlsl_lane_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlsl_lane_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlsl_laneq_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlsl_laneq_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlsl_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation
vfmlslq_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation
vfmlslq_lane_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlslq_lane_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlslq_laneq_high_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlslq_laneq_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (by element). Arm’s documentation
vfmlslq_low_f16`fhm` and `fp16` and `neon`
  Floating-point fused Multiply-Subtract Long from accumulator (vector). Arm’s documentation
vfms_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfms_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfms_f64`neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfms_lane_f16`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfms_lane_f32`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfms_lane_f64`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfms_laneq_f16`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfms_laneq_f32`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfms_laneq_f64`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfms_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation
vfms_n_f64`neon`
  Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation
vfmsd_lane_f64`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmsd_laneq_f64`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmsq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsq_f64`neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsq_lane_f16`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsq_lane_f32`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmsq_lane_f64`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmsq_laneq_f16`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsq_laneq_f32`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmsq_laneq_f64`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmsq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation
vfmsq_n_f64`neon`
  Floating-point fused Multiply-subtract to accumulator(vector) Arm’s documentation
vfmss_lane_f32`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vfmss_laneq_f32`neon`
  Floating-point fused multiply-subtract to accumulator Arm’s documentation
vget_high_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Duplicate vector element to vector Arm’s documentation
vget_high_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_f64`neon`
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_p64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_high_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_lane_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_f64`neon`
  Duplicate vector element to vector or scalar
vget_lane_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_lane_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vget_low_f16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Duplicate vector element to vector Arm’s documentation
vget_low_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_f64`neon`
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_p64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vget_low_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vgetq_lane_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_f64`neon`
  Duplicate vector element to vector or scalar Arm’s documentation
vgetq_lane_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_p64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vgetq_lane_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Move vector element to general-purpose register Arm’s documentation
vhadd_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhadd_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhadd_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhadd_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhadd_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhadd_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhaddq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhaddq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhaddq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhaddq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhaddq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhaddq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Halving add Arm’s documentation
vhsub_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsub_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsub_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsub_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsub_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsub_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsubq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsubq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsubq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsubq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsubq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vhsubq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed halving subtract Arm’s documentation
vld1_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_f64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers
vld1_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_dup_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1_f32⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f64_x2⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f64_x3⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f64_x4⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_f64⚠`neon`
  Load one single-element structure to one lane of one register.
vld1_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_lane_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1_p8⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p16⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p64⚠`aes` and `neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p64_x2⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p64_x3⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_p64_x4⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s8⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s16⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s32⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_s64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u8⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u16⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u32⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_u64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_f64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers
vld1q_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_dup_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure and Replicate to all lanes (of one register). Arm’s documentation
vld1q_f32⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f64_x2⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f64_x3⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f64_x4⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_f64⚠`neon`
  Load one single-element structure to one lane of one register.
vld1q_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_lane_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load one single-element structure to one lane of one register. Arm’s documentation
vld1q_p8⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p16⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p64⚠`aes` and `neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p64_x2⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p64_x3⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_p64_x4⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s8⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s16⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s32⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_s64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u8⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u16⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u32⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u64⚠`neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_u64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld2_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_f64⚠`neon`
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_dup_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_f64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_f64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_p64⚠`aes` and `neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_s64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_lane_u64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_f64⚠`neon`
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_p64⚠`aes` and `neon`
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_s64⚠`neon`
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_dup_u64⚠`neon`
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_f64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_f64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_p8⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_p64⚠`aes` and `neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_s8⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_s64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_u8⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_lane_u64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_p64⚠`aes` and `neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_s64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_u64⚠`neon`
  Load multiple 2-element structures to two registers Arm’s documentation
vld3_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_f64⚠`neon`
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_dup_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_f64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_f64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_p64⚠`aes` and `neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to two registers Arm’s documentation
vld3_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to two registers Arm’s documentation
vld3_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to two registers Arm’s documentation
vld3_lane_s64⚠`neon`
  Load multiple 3-element structures to two registers Arm’s documentation
vld3_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_lane_u64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_f64⚠`neon`
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_p64⚠`aes` and `neon`
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_s64⚠`neon`
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_dup_u64⚠`neon`
  Load single 3-element structure and replicate to all lanes of three registers Arm’s documentation
vld3q_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_f64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_f64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_p8⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_p64⚠`aes` and `neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_s8⚠`neon`
  Load multiple 3-element structures to two registers Arm’s documentation
vld3q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to two registers Arm’s documentation
vld3q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to two registers Arm’s documentation
vld3q_lane_s64⚠`neon`
  Load multiple 3-element structures to two registers Arm’s documentation
vld3q_lane_u8⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_lane_u64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_p64⚠`aes` and `neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_s64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 3-element structures to three registers Arm’s documentation
vld3q_u64⚠`neon`
  Load multiple 3-element structures to three registers Arm’s documentation
vld4_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_f64⚠`neon`
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_dup_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_f64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_f64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_p64⚠`aes` and `neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_s64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_lane_u64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_dup_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_f64⚠`neon`
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_p64⚠`aes` and `neon`
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_s64⚠`neon`
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_dup_u64⚠`neon`
  Load single 4-element structure and replicate to all lanes of four registers Arm’s documentation
vld4q_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_f64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_f64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_p8⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_p64⚠`aes` and `neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_s8⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_s64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_u8⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_lane_u64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_p64⚠`aes` and `neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_s64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Load multiple 4-element structures to four registers Arm’s documentation
vld4q_u64⚠`neon`
  Load multiple 4-element structures to four registers Arm’s documentation
vldrq_p128⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store SIMD&FP register (immediate offset) Arm’s documentation
vmax_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Maximum (vector) Arm’s documentation
vmax_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmax_f64`neon`
  Maximum (vector) Arm’s documentation
vmax_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmax_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmax_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmax_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmax_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmax_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxnm_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point Maximum Number (vector) Arm’s documentation
vmaxnm_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point Maximum Number (vector) Arm’s documentation
vmaxnm_f64`neon`
  Floating-point Maximum Number (vector) Arm’s documentation
vmaxnmq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point Maximum Number (vector) Arm’s documentation
vmaxnmq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point Maximum Number (vector) Arm’s documentation
vmaxnmq_f64`neon`
  Floating-point Maximum Number (vector) Arm’s documentation
vmaxnmv_f32`neon`
  Floating-point maximum number across vector Arm’s documentation
vmaxnmvq_f32`neon`
  Floating-point maximum number across vector Arm’s documentation
vmaxnmvq_f64`neon`
  Floating-point maximum number across vector Arm’s documentation
vmaxq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Maximum (vector) Arm’s documentation
vmaxq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxq_f64`neon`
  Maximum (vector) Arm’s documentation
vmaxq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Maximum (vector) Arm’s documentation
vmaxv_f32`neon`
  Horizontal vector max. Arm’s documentation
vmaxv_s8`neon`
  Horizontal vector max. Arm’s documentation
vmaxv_s16`neon`
  Horizontal vector max. Arm’s documentation
vmaxv_s32`neon`
  Horizontal vector max. Arm’s documentation
vmaxv_u8`neon`
  Horizontal vector max. Arm’s documentation
vmaxv_u16`neon`
  Horizontal vector max. Arm’s documentation
vmaxv_u32`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_f32`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_f64`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_s8`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_s16`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_s32`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_u8`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_u16`neon`
  Horizontal vector max. Arm’s documentation
vmaxvq_u32`neon`
  Horizontal vector max. Arm’s documentation
vmin_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Minimum (vector) Arm’s documentation
vmin_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vmin_f64`neon`
  Minimum (vector) Arm’s documentation
vmin_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vmin_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vmin_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vmin_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vmin_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vmin_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminnm_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point Minimum Number (vector) Arm’s documentation
vminnm_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point Minimum Number (vector) Arm’s documentation
vminnm_f64`neon`
  Floating-point Minimum Number (vector) Arm’s documentation
vminnmq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point Minimum Number (vector) Arm’s documentation
vminnmq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point Minimum Number (vector) Arm’s documentation
vminnmq_f64`neon`
  Floating-point Minimum Number (vector) Arm’s documentation
vminnmv_f32`neon`
  Floating-point minimum number across vector Arm’s documentation
vminnmvq_f32`neon`
  Floating-point minimum number across vector Arm’s documentation
vminnmvq_f64`neon`
  Floating-point minimum number across vector Arm’s documentation
vminq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Minimum (vector) Arm’s documentation
vminq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminq_f64`neon`
  Minimum (vector) Arm’s documentation
vminq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Minimum (vector) Arm’s documentation
vminv_f32`neon`
  Horizontal vector min. Arm’s documentation
vminv_s8`neon`
  Horizontal vector min. Arm’s documentation
vminv_s16`neon`
  Horizontal vector min. Arm’s documentation
vminv_s32`neon`
  Horizontal vector min. Arm’s documentation
vminv_u8`neon`
  Horizontal vector min. Arm’s documentation
vminv_u16`neon`
  Horizontal vector min. Arm’s documentation
vminv_u32`neon`
  Horizontal vector min. Arm’s documentation
vminvq_f32`neon`
  Horizontal vector min. Arm’s documentation
vminvq_f64`neon`
  Horizontal vector min. Arm’s documentation
vminvq_s8`neon`
  Horizontal vector min. Arm’s documentation
vminvq_s16`neon`
  Horizontal vector min. Arm’s documentation
vminvq_s32`neon`
  Horizontal vector min. Arm’s documentation
vminvq_u8`neon`
  Horizontal vector min. Arm’s documentation
vminvq_u16`neon`
  Horizontal vector min. Arm’s documentation
vminvq_u32`neon`
  Horizontal vector min. Arm’s documentation
vmla_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply-add to accumulator Arm’s documentation
vmla_f64`neon`
  Floating-point multiply-add to accumulator Arm’s documentation
vmla_lane_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_laneq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmla_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmla_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmla_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmla_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmla_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmla_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmlal_high_lane_s16`neon`
  Multiply-add long Arm’s documentation
vmlal_high_lane_s32`neon`
  Multiply-add long Arm’s documentation
vmlal_high_lane_u16`neon`
  Multiply-add long Arm’s documentation
vmlal_high_lane_u32`neon`
  Multiply-add long Arm’s documentation
vmlal_high_laneq_s16`neon`
  Multiply-add long Arm’s documentation
vmlal_high_laneq_s32`neon`
  Multiply-add long Arm’s documentation
vmlal_high_laneq_u16`neon`
  Multiply-add long Arm’s documentation
vmlal_high_laneq_u32`neon`
  Multiply-add long Arm’s documentation
vmlal_high_n_s16`neon`
  Multiply-add long Arm’s documentation
vmlal_high_n_s32`neon`
  Multiply-add long Arm’s documentation
vmlal_high_n_u16`neon`
  Multiply-add long Arm’s documentation
vmlal_high_n_u32`neon`
  Multiply-add long Arm’s documentation
vmlal_high_s8`neon`
  Signed multiply-add long Arm’s documentation
vmlal_high_s16`neon`
  Signed multiply-add long Arm’s documentation
vmlal_high_s32`neon`
  Signed multiply-add long Arm’s documentation
vmlal_high_u8`neon`
  Unsigned multiply-add long Arm’s documentation
vmlal_high_u16`neon`
  Unsigned multiply-add long Arm’s documentation
vmlal_high_u32`neon`
  Unsigned multiply-add long Arm’s documentation
vmlal_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply accumulate with scalar Arm’s documentation
vmlal_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply-add long Arm’s documentation
vmlal_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply-add long Arm’s documentation
vmlal_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply-add long Arm’s documentation
vmlal_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply-add long Arm’s documentation
vmlal_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply-add long Arm’s documentation
vmlal_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply-add long Arm’s documentation
vmlaq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply-add to accumulator Arm’s documentation
vmlaq_f64`neon`
  Floating-point multiply-add to accumulator Arm’s documentation
vmlaq_lane_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_laneq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply accumulate with scalar Arm’s documentation
vmlaq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmlaq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmlaq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmlaq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmlaq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmlaq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-add to accumulator Arm’s documentation
vmls_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply-subtract from accumulator Arm’s documentation
vmls_f64`neon`
  Floating-point multiply-subtract from accumulator Arm’s documentation
vmls_lane_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_laneq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmls_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmls_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmls_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmls_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmls_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmls_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmlsl_high_lane_s16`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_lane_s32`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_lane_u16`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_lane_u32`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_laneq_s16`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_laneq_s32`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_laneq_u16`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_laneq_u32`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_n_s16`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_n_s32`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_n_u16`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_n_u32`neon`
  Multiply-subtract long Arm’s documentation
vmlsl_high_s8`neon`
  Signed multiply-subtract long Arm’s documentation
vmlsl_high_s16`neon`
  Signed multiply-subtract long Arm’s documentation
vmlsl_high_s32`neon`
  Signed multiply-subtract long Arm’s documentation
vmlsl_high_u8`neon`
  Unsigned multiply-subtract long Arm’s documentation
vmlsl_high_u16`neon`
  Unsigned multiply-subtract long Arm’s documentation
vmlsl_high_u32`neon`
  Unsigned multiply-subtract long Arm’s documentation
vmlsl_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening multiply subtract with scalar Arm’s documentation
vmlsl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply-subtract long Arm’s documentation
vmlsl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply-subtract long Arm’s documentation
vmlsl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply-subtract long Arm’s documentation
vmlsl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply-subtract long Arm’s documentation
vmlsl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply-subtract long Arm’s documentation
vmlsl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply-subtract long Arm’s documentation
vmlsq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply-subtract from accumulator Arm’s documentation
vmlsq_f64`neon`
  Floating-point multiply-subtract from accumulator Arm’s documentation
vmlsq_lane_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_laneq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply subtract with scalar Arm’s documentation
vmlsq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmlsq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmlsq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmlsq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmlsq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmlsq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply-subtract from accumulator Arm’s documentation
vmov_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_f64`neon`
  Duplicate vector element to vector or scalar
vmov_n_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_p64`neon`
  Duplicate vector element to vector or scalar
vmov_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmov_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovl_high_s8`neon`
  Vector move Arm’s documentation
vmovl_high_s16`neon`
  Vector move Arm’s documentation
vmovl_high_s32`neon`
  Vector move Arm’s documentation
vmovl_high_u8`neon`
  Vector move Arm’s documentation
vmovl_high_u16`neon`
  Vector move Arm’s documentation
vmovl_high_u32`neon`
  Vector move Arm’s documentation
vmovl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long move. Arm’s documentation
vmovl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long move. Arm’s documentation
vmovl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long move. Arm’s documentation
vmovl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long move. Arm’s documentation
vmovl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long move. Arm’s documentation
vmovl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long move. Arm’s documentation
vmovn_high_s16`neon`
  Extract narrow Arm’s documentation
vmovn_high_s32`neon`
  Extract narrow Arm’s documentation
vmovn_high_s64`neon`
  Extract narrow Arm’s documentation
vmovn_high_u16`neon`
  Extract narrow Arm’s documentation
vmovn_high_u32`neon`
  Extract narrow Arm’s documentation
vmovn_high_u64`neon`
  Extract narrow Arm’s documentation
vmovn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector narrow integer. Arm’s documentation
vmovn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector narrow integer. Arm’s documentation
vmovn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector narrow integer. Arm’s documentation
vmovn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector narrow integer. Arm’s documentation
vmovn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector narrow integer. Arm’s documentation
vmovn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector narrow integer. Arm’s documentation
vmovq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_f64`neon`
  Duplicate vector element to vector or scalar
vmovq_n_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_p64`neon`
  Duplicate vector element to vector or scalar
vmovq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmovq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Duplicate vector element to vector or scalar Arm’s documentation
vmul_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Multiply Arm’s documentation
vmul_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_f64`neon`
  Multiply Arm’s documentation
vmul_lane_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Multiply Arm’s documentation
vmul_lane_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply Arm’s documentation
vmul_lane_f64`neon`
  Floating-point multiply Arm’s documentation
vmul_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_laneq_f16`fp16` and `neon`
  Floating-point multiply Arm’s documentation
vmul_laneq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply Arm’s documentation
vmul_laneq_f64`neon`
  Floating-point multiply Arm’s documentation
vmul_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmul_n_f64`neon`
  Vector multiply by scalar Arm’s documentation
vmul_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmul_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmul_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmul_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmul_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Polynomial multiply Arm’s documentation
vmul_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmul_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmuld_lane_f64`neon`
  Floating-point multiply Arm’s documentation
vmuld_laneq_f64`neon`
  Floating-point multiply Arm’s documentation
vmull_high_lane_s16`neon`
  Multiply long Arm’s documentation
vmull_high_lane_s32`neon`
  Multiply long Arm’s documentation
vmull_high_lane_u16`neon`
  Multiply long Arm’s documentation
vmull_high_lane_u32`neon`
  Multiply long Arm’s documentation
vmull_high_laneq_s16`neon`
  Multiply long Arm’s documentation
vmull_high_laneq_s32`neon`
  Multiply long Arm’s documentation
vmull_high_laneq_u16`neon`
  Multiply long Arm’s documentation
vmull_high_laneq_u32`neon`
  Multiply long Arm’s documentation
vmull_high_n_s16`neon`
  Multiply long Arm’s documentation
vmull_high_n_s32`neon`
  Multiply long Arm’s documentation
vmull_high_n_u16`neon`
  Multiply long Arm’s documentation
vmull_high_n_u32`neon`
  Multiply long Arm’s documentation
vmull_high_p8`neon`
  Polynomial multiply long Arm’s documentation
vmull_high_p64`aes` and `neon`
  Polynomial multiply long Arm’s documentation
vmull_high_s8`neon`
  Signed multiply long Arm’s documentation
vmull_high_s16`neon`
  Signed multiply long Arm’s documentation
vmull_high_s32`neon`
  Signed multiply long Arm’s documentation
vmull_high_u8`neon`
  Unsigned multiply long Arm’s documentation
vmull_high_u16`neon`
  Unsigned multiply long Arm’s documentation
vmull_high_u32`neon`
  Unsigned multiply long Arm’s documentation
vmull_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply by scalar Arm’s documentation
vmull_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply with scalar Arm’s documentation
vmull_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply with scalar Arm’s documentation
vmull_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply with scalar Arm’s documentation
vmull_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector long multiply with scalar Arm’s documentation
vmull_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Polynomial multiply long Arm’s documentation
vmull_p64`aes` and `neon`
  Polynomial multiply long Arm’s documentation
vmull_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply long Arm’s documentation
vmull_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply long Arm’s documentation
vmull_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed multiply long Arm’s documentation
vmull_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply long Arm’s documentation
vmull_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply long Arm’s documentation
vmull_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned multiply long Arm’s documentation
vmulq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Multiply Arm’s documentation
vmulq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_f64`neon`
  Multiply Arm’s documentation
vmulq_lane_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Multiply Arm’s documentation
vmulq_lane_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply Arm’s documentation
vmulq_lane_f64`neon`
  Floating-point multiply Arm’s documentation
vmulq_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_lane_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_lane_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_laneq_f16`fp16` and `neon`
  Floating-point multiply Arm’s documentation
vmulq_laneq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point multiply Arm’s documentation
vmulq_laneq_f64`neon`
  Floating-point multiply Arm’s documentation
vmulq_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_laneq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_laneq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_n_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmulq_n_f64`neon`
  Vector multiply by scalar Arm’s documentation
vmulq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmulq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmulq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmulq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector multiply by scalar Arm’s documentation
vmulq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Polynomial multiply Arm’s documentation
vmulq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmulq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Multiply Arm’s documentation
vmuls_lane_f32`neon`
  Floating-point multiply Arm’s documentation
vmuls_laneq_f32`neon`
  Floating-point multiply Arm’s documentation
vmulx_f16`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulx_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulx_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulx_lane_f16`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulx_lane_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulx_lane_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulx_laneq_f16`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulx_laneq_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulx_laneq_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxd_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxd_lane_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxd_laneq_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_f16`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_lane_f16`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_lane_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_lane_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_laneq_f16`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_laneq_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_laneq_f64`neon`
  Floating-point multiply extended Arm’s documentation
vmulxs_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulxs_lane_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmulxs_laneq_f32`neon`
  Floating-point multiply extended Arm’s documentation
vmvn_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvn_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvn_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vmvnq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise not. Arm’s documentation
vneg_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Negate Arm’s documentation
vneg_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vneg_f64`neon`
  Negate Arm’s documentation
vneg_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vneg_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vneg_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vneg_s64`neon`
  Negate Arm’s documentation
vnegd_s64`neon`
  Negate Arm’s documentation
vnegq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Negate Arm’s documentation
vnegq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vnegq_f64`neon`
  Negate Arm’s documentation
vnegq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vnegq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vnegq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Negate Arm’s documentation
vnegq_s64`neon`
  Negate Arm’s documentation
vorn_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vornq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise inclusive OR NOT Arm’s documentation
vorr_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorr_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vorrq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector bitwise or (immediate, inclusive) Arm’s documentation
vpadal_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpadal_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpadal_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpadal_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpadal_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpadal_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpadalq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpadalq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpadalq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpadalq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpadalq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpadalq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpadd_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point add pairwise Arm’s documentation
vpadd_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point add pairwise Arm’s documentation
vpadd_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add pairwise. Arm’s documentation
vpadd_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add pairwise. Arm’s documentation
vpadd_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add pairwise. Arm’s documentation
vpadd_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add pairwise. Arm’s documentation
vpadd_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add pairwise. Arm’s documentation
vpadd_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Add pairwise. Arm’s documentation
vpaddd_f64`neon`
  Floating-point add pairwise Arm’s documentation
vpaddd_s64`neon`
  Add pairwise Arm’s documentation
vpaddd_u64`neon`
  Add pairwise Arm’s documentation
vpaddl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpaddl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpaddl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpaddl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpaddl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpaddl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpaddlq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpaddlq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpaddlq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Add and Accumulate Long Pairwise. Arm’s documentation
vpaddlq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpaddlq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpaddlq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Add and Accumulate Long Pairwise. Arm’s documentation
vpaddq_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpaddq_f32`neon`
  Floating-point add pairwise Arm’s documentation
vpaddq_f64`neon`
  Floating-point add pairwise Arm’s documentation
vpaddq_s8`neon`
  Add Pairwise Arm’s documentation
vpaddq_s16`neon`
  Add Pairwise Arm’s documentation
vpaddq_s32`neon`
  Add Pairwise Arm’s documentation
vpaddq_s64`neon`
  Add Pairwise Arm’s documentation
vpaddq_u8`neon`
  Add Pairwise Arm’s documentation
vpaddq_u16`neon`
  Add Pairwise Arm’s documentation
vpaddq_u32`neon`
  Add Pairwise Arm’s documentation
vpaddq_u64`neon`
  Add Pairwise Arm’s documentation
vpadds_f32`neon`
  Floating-point add pairwise Arm’s documentation
vpmax_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpmax_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmax_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmax_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmax_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmax_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmax_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmax_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxnm_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpmaxnm_f32`neon`
  Floating-point Maximum Number Pairwise (vector). Arm’s documentation
vpmaxnmq_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpmaxnmq_f32`neon`
  Floating-point Maximum Number Pairwise (vector). Arm’s documentation
vpmaxnmq_f64`neon`
  Floating-point Maximum Number Pairwise (vector). Arm’s documentation
vpmaxnmqd_f64`neon`
  Floating-point maximum number pairwise Arm’s documentation
vpmaxnms_f32`neon`
  Floating-point maximum number pairwise Arm’s documentation
vpmaxq_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpmaxq_f32`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_f64`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_s8`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_s16`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_s32`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_u8`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_u16`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxq_u32`neon`
  Folding maximum of adjacent pairs Arm’s documentation
vpmaxqd_f64`neon`
  Floating-point maximum pairwise Arm’s documentation
vpmaxs_f32`neon`
  Floating-point maximum pairwise Arm’s documentation
vpmin_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpmin_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpmin_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpmin_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpmin_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpmin_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpmin_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpmin_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Folding minimum of adjacent pairs Arm’s documentation
vpminnm_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpminnm_f32`neon`
  Floating-point Minimum Number Pairwise (vector). Arm’s documentation
vpminnmq_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpminnmq_f32`neon`
  Floating-point Minimum Number Pairwise (vector). Arm’s documentation
vpminnmq_f64`neon`
  Floating-point Minimum Number Pairwise (vector). Arm’s documentation
vpminnmqd_f64`neon`
  Floating-point minimum number pairwise Arm’s documentation
vpminnms_f32`neon`
  Floating-point minimum number pairwise Arm’s documentation
vpminq_f16`fp16` and `neon`
  Floating-point add pairwise Arm’s documentation
vpminq_f32`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_f64`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_s8`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_s16`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_s32`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_u8`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_u16`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminq_u32`neon`
  Folding minimum of adjacent pairs Arm’s documentation
vpminqd_f64`neon`
  Floating-point minimum pairwise Arm’s documentation
vpmins_f32`neon`
  Floating-point minimum pairwise Arm’s documentation
vqabs_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating Absolute value Arm’s documentation
vqabs_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating Absolute value Arm’s documentation
vqabs_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating Absolute value Arm’s documentation
vqabs_s64`neon`
  Signed saturating Absolute value Arm’s documentation
vqabsb_s8`neon`
  Signed saturating absolute value Arm’s documentation
vqabsd_s64`neon`
  Signed saturating absolute value Arm’s documentation
vqabsh_s16`neon`
  Signed saturating absolute value Arm’s documentation
vqabsq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating Absolute value Arm’s documentation
vqabsq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating Absolute value Arm’s documentation
vqabsq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating Absolute value Arm’s documentation
vqabsq_s64`neon`
  Signed saturating Absolute value Arm’s documentation
vqabss_s32`neon`
  Signed saturating absolute value Arm’s documentation
vqadd_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadd_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddb_s8`neon`
  Saturating add Arm’s documentation
vqaddb_u8`neon`
  Saturating add Arm’s documentation
vqaddd_s64`neon`
  Saturating add Arm’s documentation
vqaddd_u64`neon`
  Saturating add Arm’s documentation
vqaddh_s16`neon`
  Saturating add Arm’s documentation
vqaddh_u16`neon`
  Saturating add Arm’s documentation
vqaddq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqaddq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating add Arm’s documentation
vqadds_s32`neon`
  Saturating add Arm’s documentation
vqadds_u32`neon`
  Saturating add Arm’s documentation
vqdmlal_high_lane_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_lane_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_laneq_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_laneq_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_n_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_n_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_high_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation
vqdmlal_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation
vqdmlal_laneq_s16`neon`
  Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation
vqdmlal_laneq_s32`neon`
  Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation
vqdmlal_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation
vqdmlal_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply accumulate with scalar Arm’s documentation
vqdmlal_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlal_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlalh_lane_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlalh_laneq_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlalh_s16`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlals_lane_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlals_laneq_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlals_s32`neon`
  Signed saturating doubling multiply-add long Arm’s documentation
vqdmlsl_high_lane_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_lane_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_laneq_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_laneq_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_n_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_n_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_high_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply subtract with scalar Arm’s documentation
vqdmlsl_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply subtract with scalar Arm’s documentation
vqdmlsl_laneq_s16`neon`
  Vector widening saturating doubling multiply subtract with scalar Arm’s documentation
vqdmlsl_laneq_s32`neon`
  Vector widening saturating doubling multiply subtract with scalar Arm’s documentation
vqdmlsl_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply subtract with scalar Arm’s documentation
vqdmlsl_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector widening saturating doubling multiply subtract with scalar Arm’s documentation
vqdmlsl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlslh_lane_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlslh_laneq_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlslh_s16`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsls_lane_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsls_laneq_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmlsls_s32`neon`
  Signed saturating doubling multiply-subtract long Arm’s documentation
vqdmulh_lane_s16`neon`
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulh_lane_s32`neon`
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulh_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulh_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulh_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high with scalar Arm’s documentation
vqdmulh_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high with scalar Arm’s documentation
vqdmulh_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulh_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhh_lane_s16`neon`
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhh_laneq_s16`neon`
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhh_s16`neon`
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhq_lane_s16`neon`
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulhq_lane_s32`neon`
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulhq_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulhq_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high by scalar Arm’s documentation
vqdmulhq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high with scalar Arm’s documentation
vqdmulhq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling multiply high with scalar Arm’s documentation
vqdmulhq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhs_lane_s32`neon`
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhs_laneq_s32`neon`
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmulhs_s32`neon`
  Signed saturating doubling multiply returning high half Arm’s documentation
vqdmull_high_lane_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_lane_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_laneq_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_laneq_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_n_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_n_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_high_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling long multiply by scalar Arm’s documentation
vqdmull_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling long multiply by scalar Arm’s documentation
vqdmull_laneq_s16`neon`
  Vector saturating doubling long multiply by scalar Arm’s documentation
vqdmull_laneq_s32`neon`
  Vector saturating doubling long multiply by scalar Arm’s documentation
vqdmull_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling long multiply with scalar Arm’s documentation
vqdmull_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating doubling long multiply with scalar Arm’s documentation
vqdmull_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply long Arm’s documentation
vqdmull_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating doubling multiply long Arm’s documentation
vqdmullh_lane_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmullh_laneq_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmullh_s16`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmulls_lane_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmulls_laneq_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqdmulls_s32`neon`
  Signed saturating doubling multiply long Arm’s documentation
vqmovn_high_s16`neon`
  Signed saturating extract narrow Arm’s documentation
vqmovn_high_s32`neon`
  Signed saturating extract narrow Arm’s documentation
vqmovn_high_s64`neon`
  Signed saturating extract narrow Arm’s documentation
vqmovn_high_u16`neon`
  Signed saturating extract narrow Arm’s documentation
vqmovn_high_u32`neon`
  Signed saturating extract narrow Arm’s documentation
vqmovn_high_u64`neon`
  Signed saturating extract narrow Arm’s documentation
vqmovn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating extract narrow Arm’s documentation
vqmovn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating extract narrow Arm’s documentation
vqmovn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating extract narrow Arm’s documentation
vqmovn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating extract narrow Arm’s documentation
vqmovn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating extract narrow Arm’s documentation
vqmovn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating extract narrow Arm’s documentation
vqmovnd_s64`neon`
  Saturating extract narrow Arm’s documentation
vqmovnd_u64`neon`
  Saturating extract narrow Arm’s documentation
vqmovnh_s16`neon`
  Saturating extract narrow Arm’s documentation
vqmovnh_u16`neon`
  Saturating extract narrow Arm’s documentation
vqmovns_s32`neon`
  Saturating extract narrow Arm’s documentation
vqmovns_u32`neon`
  Saturating extract narrow Arm’s documentation
vqmovun_high_s16`neon`
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovun_high_s32`neon`
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovun_high_s64`neon`
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovun_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovun_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovun_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovund_s64`neon`
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovunh_s16`neon`
  Signed saturating extract unsigned narrow Arm’s documentation
vqmovuns_s32`neon`
  Signed saturating extract unsigned narrow Arm’s documentation
vqneg_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating negate Arm’s documentation
vqneg_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating negate Arm’s documentation
vqneg_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating negate Arm’s documentation
vqneg_s64`neon`
  Signed saturating negate Arm’s documentation
vqnegb_s8`neon`
  Signed saturating negate Arm’s documentation
vqnegd_s64`neon`
  Signed saturating negate Arm’s documentation
vqnegh_s16`neon`
  Signed saturating negate Arm’s documentation
vqnegq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating negate Arm’s documentation
vqnegq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating negate Arm’s documentation
vqnegq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating negate Arm’s documentation
vqnegq_s64`neon`
  Signed saturating negate Arm’s documentation
vqnegs_s32`neon`
  Signed saturating negate Arm’s documentation
vqrdmlah_lane_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlah_lane_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlah_laneq_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlah_laneq_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlah_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlah_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahh_lane_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahh_laneq_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahh_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahq_lane_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahq_lane_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahq_laneq_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahq_laneq_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahq_s16`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahq_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahs_lane_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahs_laneq_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlahs_s32`rdm`
  Signed saturating rounding doubling multiply accumulate returning high half Arm’s documentation
vqrdmlsh_lane_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlsh_lane_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlsh_laneq_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlsh_laneq_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlsh_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlsh_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshh_lane_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshh_laneq_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshh_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshq_lane_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshq_lane_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshq_laneq_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshq_laneq_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshq_s16`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshq_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshs_lane_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshs_laneq_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmlshs_s32`rdm`
  Signed saturating rounding doubling multiply subtract returning high half Arm’s documentation
vqrdmulh_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulh_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulh_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulh_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulh_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating rounding doubling multiply high with scalar Arm’s documentation
vqrdmulh_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating rounding doubling multiply high with scalar Arm’s documentation
vqrdmulh_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulh_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhh_lane_s16`neon`
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhh_laneq_s16`neon`
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhh_s16`neon`
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhq_lane_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulhq_lane_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulhq_laneq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulhq_laneq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector rounding saturating doubling multiply high by scalar Arm’s documentation
vqrdmulhq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating rounding doubling multiply high with scalar Arm’s documentation
vqrdmulhq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector saturating rounding doubling multiply high with scalar Arm’s documentation
vqrdmulhq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhs_lane_s32`neon`
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhs_laneq_s32`neon`
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrdmulhs_s32`neon`
  Signed saturating rounding doubling multiply returning high half Arm’s documentation
vqrshl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshl_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshl_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshlb_s8`neon`
  Signed saturating rounding shift left Arm’s documentation
vqrshlb_u8`neon`
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshld_s64`neon`
  Signed saturating rounding shift left Arm’s documentation
vqrshld_u64`neon`
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshlh_s16`neon`
  Signed saturating rounding shift left Arm’s documentation
vqrshlh_u16`neon`
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshlq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshlq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshlq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshlq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating rounding shift left Arm’s documentation
vqrshlq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshlq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshlq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshlq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshls_s32`neon`
  Signed saturating rounding shift left Arm’s documentation
vqrshls_u32`neon`
  Unsigned signed saturating rounding shift left Arm’s documentation
vqrshrn_high_n_s16`neon`
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_high_n_s32`neon`
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_high_n_s64`neon`
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_high_n_u16`neon`
  Unsigned saturating rounded shift right narrow Arm’s documentation
vqrshrn_high_n_u32`neon`
  Unsigned saturating rounded shift right narrow Arm’s documentation
vqrshrn_high_n_u64`neon`
  Unsigned saturating rounded shift right narrow Arm’s documentation
vqrshrn_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Unsigned signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Unsigned signed saturating rounded shift right narrow Arm’s documentation
vqrshrn_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Unsigned signed saturating rounded shift right narrow Arm’s documentation
vqrshrnd_n_s64`neon`
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrnd_n_u64`neon`
  Unsigned saturating rounded shift right narrow Arm’s documentation
vqrshrnh_n_s16`neon`
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrnh_n_u16`neon`
  Unsigned saturating rounded shift right narrow Arm’s documentation
vqrshrns_n_s32`neon`
  Signed saturating rounded shift right narrow Arm’s documentation
vqrshrns_n_u32`neon`
  Unsigned saturating rounded shift right narrow Arm’s documentation
vqrshrun_high_n_s16`neon`
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrun_high_n_s32`neon`
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrun_high_n_s64`neon`
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrun_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrun_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrun_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrund_n_s64`neon`
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshrunh_n_s16`neon`
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqrshruns_n_s32`neon`
  Signed saturating rounded shift right unsigned narrow Arm’s documentation
vqshl_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshl_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlb_n_s8`neon`
  Signed saturating shift left Arm’s documentation
vqshlb_n_u8`neon`
  Unsigned saturating shift left Arm’s documentation
vqshlb_s8`neon`
  Signed saturating shift left Arm’s documentation
vqshlb_u8`neon`
  Unsigned saturating shift left Arm’s documentation
vqshld_n_s64`neon`
  Signed saturating shift left Arm’s documentation
vqshld_n_u64`neon`
  Unsigned saturating shift left Arm’s documentation
vqshld_s64`neon`
  Signed saturating shift left Arm’s documentation
vqshld_u64`neon`
  Unsigned saturating shift left Arm’s documentation
vqshlh_n_s16`neon`
  Signed saturating shift left Arm’s documentation
vqshlh_n_u16`neon`
  Unsigned saturating shift left Arm’s documentation
vqshlh_s16`neon`
  Signed saturating shift left Arm’s documentation
vqshlh_u16`neon`
  Unsigned saturating shift left Arm’s documentation
vqshlq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed saturating shift left Arm’s documentation
vqshlq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshlq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned saturating shift left Arm’s documentation
vqshls_n_s32`neon`
  Signed saturating shift left Arm’s documentation
vqshls_n_u32`neon`
  Unsigned saturating shift left Arm’s documentation
vqshls_s32`neon`
  Signed saturating shift left Arm’s documentation
vqshls_u32`neon`
  Unsigned saturating shift left Arm’s documentation
vqshlu_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshlu_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshlu_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshlu_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshlub_n_s8`neon`
  Signed saturating shift left unsigned Arm’s documentation
vqshlud_n_s64`neon`
  Signed saturating shift left unsigned Arm’s documentation
vqshluh_n_s16`neon`
  Signed saturating shift left unsigned Arm’s documentation
vqshluq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshluq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshluq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshluq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift left unsigned Arm’s documentation
vqshlus_n_s32`neon`
  Signed saturating shift left unsigned Arm’s documentation
vqshrn_high_n_s16`neon`
  Signed saturating shift right narrow Arm’s documentation
vqshrn_high_n_s32`neon`
  Signed saturating shift right narrow Arm’s documentation
vqshrn_high_n_s64`neon`
  Signed saturating shift right narrow Arm’s documentation
vqshrn_high_n_u16`neon`
  Unsigned saturating shift right narrow Arm’s documentation
vqshrn_high_n_u32`neon`
  Unsigned saturating shift right narrow Arm’s documentation
vqshrn_high_n_u64`neon`
  Unsigned saturating shift right narrow Arm’s documentation
vqshrn_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift right narrow Arm’s documentation
vqshrn_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift right narrow Arm’s documentation
vqshrn_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift right narrow Arm’s documentation
vqshrn_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Unsigned saturating shift right narrow Arm’s documentation
vqshrn_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Unsigned saturating shift right narrow Arm’s documentation
vqshrn_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Unsigned saturating shift right narrow Arm’s documentation
vqshrnd_n_s64`neon`
  Signed saturating shift right narrow Arm’s documentation
vqshrnd_n_u64`neon`
  Unsigned saturating shift right narrow Arm’s documentation
vqshrnh_n_s16`neon`
  Signed saturating shift right narrow Arm’s documentation
vqshrnh_n_u16`neon`
  Unsigned saturating shift right narrow Arm’s documentation
vqshrns_n_s32`neon`
  Signed saturating shift right narrow Arm’s documentation
vqshrns_n_u32`neon`
  Unsigned saturating shift right narrow Arm’s documentation
vqshrun_high_n_s16`neon`
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrun_high_n_s32`neon`
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrun_high_n_s64`neon`
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrun_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrun_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrun_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrund_n_s64`neon`
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshrunh_n_s16`neon`
  Signed saturating shift right unsigned narrow Arm’s documentation
vqshruns_n_s32`neon`
  Signed saturating shift right unsigned narrow Arm’s documentation
vqsub_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsub_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubb_s8`neon`
  Saturating subtract Arm’s documentation
vqsubb_u8`neon`
  Saturating subtract Arm’s documentation
vqsubd_s64`neon`
  Saturating subtract Arm’s documentation
vqsubd_u64`neon`
  Saturating subtract Arm’s documentation
vqsubh_s16`neon`
  Saturating subtract Arm’s documentation
vqsubh_u16`neon`
  Saturating subtract Arm’s documentation
vqsubq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Saturating subtract Arm’s documentation
vqsubs_s32`neon`
  Saturating subtract Arm’s documentation
vqsubs_u32`neon`
  Saturating subtract Arm’s documentation
vqtbl1_p8`neon`
  Table look-up Arm’s documentation
vqtbl1_s8`neon`
  Table look-up Arm’s documentation
vqtbl1_u8`neon`
  Table look-up Arm’s documentation
vqtbl1q_p8`neon`
  Table look-up Arm’s documentation
vqtbl1q_s8`neon`
  Table look-up Arm’s documentation
vqtbl1q_u8`neon`
  Table look-up Arm’s documentation
vqtbl2_p8`neon`
  Table look-up Arm’s documentation
vqtbl2_s8`neon`
  Table look-up Arm’s documentation
vqtbl2_u8`neon`
  Table look-up Arm’s documentation
vqtbl2q_p8`neon`
  Table look-up Arm’s documentation
vqtbl2q_s8`neon`
  Table look-up Arm’s documentation
vqtbl2q_u8`neon`
  Table look-up Arm’s documentation
vqtbl3_p8`neon`
  Table look-up Arm’s documentation
vqtbl3_s8`neon`
  Table look-up Arm’s documentation
vqtbl3_u8`neon`
  Table look-up Arm’s documentation
vqtbl3q_p8`neon`
  Table look-up Arm’s documentation
vqtbl3q_s8`neon`
  Table look-up Arm’s documentation
vqtbl3q_u8`neon`
  Table look-up Arm’s documentation
vqtbl4_p8`neon`
  Table look-up Arm’s documentation
vqtbl4_s8`neon`
  Table look-up Arm’s documentation
vqtbl4_u8`neon`
  Table look-up Arm’s documentation
vqtbl4q_p8`neon`
  Table look-up Arm’s documentation
vqtbl4q_s8`neon`
  Table look-up Arm’s documentation
vqtbl4q_u8`neon`
  Table look-up Arm’s documentation
vqtbx1_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx1_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx1_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx1q_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx1q_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx1q_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx2_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx2_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx2_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx2q_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx2q_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx2q_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx3_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx3_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx3_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx3q_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx3q_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx3q_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx4_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx4_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx4_u8`neon`
  Extended table look-up Arm’s documentation
vqtbx4q_p8`neon`
  Extended table look-up Arm’s documentation
vqtbx4q_s8`neon`
  Extended table look-up Arm’s documentation
vqtbx4q_u8`neon`
  Extended table look-up Arm’s documentation
vraddhn_high_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow (high half). Arm’s documentation
vraddhn_high_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow (high half). Arm’s documentation
vraddhn_high_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow (high half). Arm’s documentation
vraddhn_high_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow (high half). Arm’s documentation
vraddhn_high_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow (high half). Arm’s documentation
vraddhn_high_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow (high half). Arm’s documentation
vraddhn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow. Arm’s documentation
vraddhn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow. Arm’s documentation
vraddhn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow. Arm’s documentation
vraddhn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow. Arm’s documentation
vraddhn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow. Arm’s documentation
vraddhn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding Add returning High Narrow. Arm’s documentation
vrax1q_u64`neon` and `sha3`
  Rotate and exclusive OR Arm’s documentation
vrbit_p8`neon`
  Reverse bit order Arm’s documentation
vrbit_s8`neon`
  Reverse bit order Arm’s documentation
vrbit_u8`neon`
  Reverse bit order Arm’s documentation
vrbitq_p8`neon`
  Reverse bit order Arm’s documentation
vrbitq_s8`neon`
  Reverse bit order Arm’s documentation
vrbitq_u8`neon`
  Reverse bit order Arm’s documentation
vrecpe_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Reciprocal estimate. Arm’s documentation
vrecpe_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reciprocal estimate. Arm’s documentation
vrecpe_f64`neon`
  Reciprocal estimate. Arm’s documentation
vrecpe_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned reciprocal estimate Arm’s documentation
vrecped_f64`neon`
  Reciprocal estimate. Arm’s documentation
vrecpeq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Reciprocal estimate. Arm’s documentation
vrecpeq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reciprocal estimate. Arm’s documentation
vrecpeq_f64`neon`
  Reciprocal estimate. Arm’s documentation
vrecpeq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned reciprocal estimate Arm’s documentation
vrecpes_f32`neon`
  Reciprocal estimate. Arm’s documentation
vrecps_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point reciprocal step Arm’s documentation
vrecps_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point reciprocal step Arm’s documentation
vrecps_f64`neon`
  Floating-point reciprocal step Arm’s documentation
vrecpsd_f64`neon`
  Floating-point reciprocal step Arm’s documentation
vrecpsq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point reciprocal step Arm’s documentation
vrecpsq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point reciprocal step Arm’s documentation
vrecpsq_f64`neon`
  Floating-point reciprocal step Arm’s documentation
vrecpss_f32`neon`
  Floating-point reciprocal step Arm’s documentation
vrecpxd_f64`neon`
  Floating-point reciprocal exponent Arm’s documentation
vrecpxs_f32`neon`
  Floating-point reciprocal exponent Arm’s documentation
vreinterpret_f16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f32_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_f16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_f32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_p8`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_p16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_s8`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_s16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_s32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_s64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_u8`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_u16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_u32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_f64_u64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p8_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_f32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_s64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_p64_u64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s8_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s32_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_s64_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u8_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u32_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpret_u64_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_p128`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_p128`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f32_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_f16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_f32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_p8`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_p16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_p128`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_s8`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_s16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_s32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_s64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_u8`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_u16`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_u32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_f64_u64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p8_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_f32`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_s64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p64_u64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_p64`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_p128_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s8_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s32_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_s64_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u8_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u16_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_p64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u32_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_f16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_f64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_p64`neon`
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_p128`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vreinterpretq_u64_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Vector reinterpret cast operation Arm’s documentation
vrev16_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev16_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev16_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev16q_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev16q_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev16q_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32q_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32q_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32q_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32q_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32q_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev32q_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Reverse elements in 64-bit doublewords Arm’s documentation
vrev64_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Reverse elements in 64-bit doublewords Arm’s documentation
vrev64q_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrev64q_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reversing vector elements (swap endianness) Arm’s documentation
vrhadd_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhadd_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhadd_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhadd_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhadd_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhadd_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhaddq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhaddq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhaddq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhaddq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhaddq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrhaddq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding halving add Arm’s documentation
vrnd_f16`fp16` and `neon`
  Floating-point round to integral, toward zero Arm’s documentation
vrnd_f32`neon`
  Floating-point round to integral, toward zero Arm’s documentation
vrnd_f64`neon`
  Floating-point round to integral, toward zero Arm’s documentation
vrnda_f16`fp16` and `neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrnda_f32`neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrnda_f64`neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrndaq_f16`fp16` and `neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrndaq_f32`neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrndaq_f64`neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrndi_f16`fp16` and `neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndi_f32`neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndi_f64`neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndiq_f16`fp16` and `neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndiq_f32`neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndiq_f64`neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndm_f16`fp16` and `neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndm_f32`neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndm_f64`neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndmq_f16`fp16` and `neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndmq_f32`neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndmq_f64`neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndn_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndn_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndn_f64`neon`
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndnq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndnq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndnq_f64`neon`
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndns_f32`neon`
  Floating-point round to integral, to nearest with ties to even Arm’s documentation
vrndp_f16`fp16` and `neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndp_f32`neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndp_f64`neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndpq_f16`fp16` and `neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndpq_f32`neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndpq_f64`neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndq_f16`fp16` and `neon`
  Floating-point round to integral, toward zero Arm’s documentation
vrndq_f32`neon`
  Floating-point round to integral, toward zero Arm’s documentation
vrndq_f64`neon`
  Floating-point round to integral, toward zero Arm’s documentation
vrndx_f16`fp16` and `neon`
  Floating-point round to integral exact, using current rounding mode Arm’s documentation
vrndx_f32`neon`
  Floating-point round to integral exact, using current rounding mode Arm’s documentation
vrndx_f64`neon`
  Floating-point round to integral exact, using current rounding mode Arm’s documentation
vrndxq_f16`fp16` and `neon`
  Floating-point round to integral exact, using current rounding mode Arm’s documentation
vrndxq_f32`neon`
  Floating-point round to integral exact, using current rounding mode Arm’s documentation
vrndxq_f64`neon`
  Floating-point round to integral exact, using current rounding mode Arm’s documentation
vrshl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshl_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshl_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshld_s64`neon`
  Signed rounding shift left Arm’s documentation
vrshld_u64`neon`
  Unsigned rounding shift left Arm’s documentation
vrshlq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshlq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshlq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshlq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift left Arm’s documentation
vrshlq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshlq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshlq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshlq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift left Arm’s documentation
vrshr_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshr_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshr_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshr_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshr_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshr_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshr_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshr_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshrd_n_s64`neon`
  Signed rounding shift right Arm’s documentation
vrshrd_n_u64`neon`
  Unsigned rounding shift right Arm’s documentation
vrshrn_high_n_s16`neon`
  Rounding shift right narrow Arm’s documentation
vrshrn_high_n_s32`neon`
  Rounding shift right narrow Arm’s documentation
vrshrn_high_n_s64`neon`
  Rounding shift right narrow Arm’s documentation
vrshrn_high_n_u16`neon`
  Rounding shift right narrow Arm’s documentation
vrshrn_high_n_u32`neon`
  Rounding shift right narrow Arm’s documentation
vrshrn_high_n_u64`neon`
  Rounding shift right narrow Arm’s documentation
vrshrn_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Rounding shift right narrow Arm’s documentation
vrshrn_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Rounding shift right narrow Arm’s documentation
vrshrn_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Rounding shift right narrow Arm’s documentation
vrshrn_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding shift right narrow Arm’s documentation
vrshrn_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding shift right narrow Arm’s documentation
vrshrn_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding shift right narrow Arm’s documentation
vrshrq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshrq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshrq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshrq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right Arm’s documentation
vrshrq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshrq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshrq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrshrq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right Arm’s documentation
vrsqrte_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Reciprocal square-root estimate. Arm’s documentation
vrsqrte_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reciprocal square-root estimate. Arm’s documentation
vrsqrte_f64`neon`
  Reciprocal square-root estimate. Arm’s documentation
vrsqrte_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned reciprocal square root estimate Arm’s documentation
vrsqrted_f64`neon`
  Reciprocal square-root estimate. Arm’s documentation
vrsqrteq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Reciprocal square-root estimate. Arm’s documentation
vrsqrteq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Reciprocal square-root estimate. Arm’s documentation
vrsqrteq_f64`neon`
  Reciprocal square-root estimate. Arm’s documentation
vrsqrteq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned reciprocal square root estimate Arm’s documentation
vrsqrtes_f32`neon`
  Reciprocal square-root estimate. Arm’s documentation
vrsqrts_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point reciprocal square root step Arm’s documentation
vrsqrts_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point reciprocal square root step Arm’s documentation
vrsqrts_f64`neon`
  Floating-point reciprocal square root step Arm’s documentation
vrsqrtsd_f64`neon`
  Floating-point reciprocal square root step Arm’s documentation
vrsqrtsq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point reciprocal square root step Arm’s documentation
vrsqrtsq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Floating-point reciprocal square root step Arm’s documentation
vrsqrtsq_f64`neon`
  Floating-point reciprocal square root step Arm’s documentation
vrsqrtss_f32`neon`
  Floating-point reciprocal square root step Arm’s documentation
vrsra_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsra_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsra_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsra_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsra_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsra_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsra_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsra_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsrad_n_s64`neon`
  Signed rounding shift right and accumulate. Arm’s documentation
vrsrad_n_u64`neon`
  Unsigned rounding shift right and accumulate. Arm’s documentation
vrsraq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsraq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsraq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsraq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed rounding shift right and accumulate Arm’s documentation
vrsraq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsraq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsraq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsraq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned rounding shift right and accumulate Arm’s documentation
vrsubhn_high_s16`neon`
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_high_s32`neon`
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_high_s64`neon`
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_high_u16`neon`
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_high_u32`neon`
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_high_u64`neon`
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding subtract returning high narrow Arm’s documentation
vrsubhn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Rounding subtract returning high narrow Arm’s documentation
vset_lane_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vset_lane_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_p64`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vset_lane_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_f64`neon`
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_p64Little-endian and `aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_s64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_u64Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Insert vector element from another vector element Arm’s documentation
vsha1cq_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 hash update accelerator, choose. Arm’s documentation
vsha1h_u32`sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 fixed rotate. Arm’s documentation
vsha1mq_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 hash update accelerator, majority Arm’s documentation
vsha1pq_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 hash update accelerator, parity Arm’s documentation
vsha1su0q_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 schedule update accelerator, first part. Arm’s documentation
vsha1su1q_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 schedule update accelerator, second part. Arm’s documentation
vsha256h2q_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 schedule update accelerator, upper part. Arm’s documentation
vsha256hq_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA1 schedule update accelerator, first part. Arm’s documentation
vsha256su0q_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA256 schedule update accelerator, first part. Arm’s documentation
vsha256su1q_u32Little-endian and `sha2` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  SHA256 schedule update accelerator, second part. Arm’s documentation
vsha512h2q_u64`neon` and `sha3`
  SHA512 hash update part 2 Arm’s documentation
vsha512hq_u64`neon` and `sha3`
  SHA512 hash update part 1 Arm’s documentation
vsha512su0q_u64`neon` and `sha3`
  SHA512 schedule update 0 Arm’s documentation
vsha512su1q_u64`neon` and `sha3`
  SHA512 schedule update 1 Arm’s documentation
vshl_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshl_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshl_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshld_n_s64`neon`
  Shift left
vshld_n_u64`neon`
  Shift left
vshld_s64`neon`
  Signed Shift left Arm’s documentation
vshld_u64`neon`
  Unsigned Shift left Arm’s documentation
vshll_high_n_s8`neon`
  Signed shift left long Arm’s documentation
vshll_high_n_s16`neon`
  Signed shift left long Arm’s documentation
vshll_high_n_s32`neon`
  Signed shift left long Arm’s documentation
vshll_high_n_u8`neon`
  Signed shift left long Arm’s documentation
vshll_high_n_u16`neon`
  Signed shift left long Arm’s documentation
vshll_high_n_u32`neon`
  Signed shift left long Arm’s documentation
vshll_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift left long Arm’s documentation
vshll_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift left long Arm’s documentation
vshll_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift left long Arm’s documentation
vshll_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift left long Arm’s documentation
vshll_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift left long Arm’s documentation
vshll_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift left long Arm’s documentation
vshlq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift left Arm’s documentation
vshlq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshlq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshlq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshlq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Shift left Arm’s documentation
vshlq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshlq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshlq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshlq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Shift left Arm’s documentation
vshr_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshr_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrd_n_s64`neon`
  Signed shift right
vshrd_n_u64`neon`
  Unsigned shift right
vshrn_high_n_s16`neon`
  Shift right narrow Arm’s documentation
vshrn_high_n_s32`neon`
  Shift right narrow Arm’s documentation
vshrn_high_n_s64`neon`
  Shift right narrow Arm’s documentation
vshrn_high_n_u16`neon`
  Shift right narrow Arm’s documentation
vshrn_high_n_u32`neon`
  Shift right narrow Arm’s documentation
vshrn_high_n_u64`neon`
  Shift right narrow Arm’s documentation
vshrn_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right narrow Arm’s documentation
vshrn_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right narrow Arm’s documentation
vshrn_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right narrow Arm’s documentation
vshrn_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right narrow Arm’s documentation
vshrn_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right narrow Arm’s documentation
vshrn_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right narrow Arm’s documentation
vshrq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vshrq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Shift right Arm’s documentation
vsli_n_p8`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_p16`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_p64`aes` and `neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_s8`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_s16`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_s32`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_s64`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_u8`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_u16`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_u32`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsli_n_u64`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vslid_n_s64`neon`
  Shift left and insert Arm’s documentation
vslid_n_u64`neon`
  Shift left and insert Arm’s documentation
vsliq_n_p8`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_p16`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_p64`aes` and `neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_s8`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_s16`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_s32`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_s64`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_u8`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_u16`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_u32`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsliq_n_u64`neon`
  Shift Left and Insert (immediate) Arm’s documentation
vsqadd_u8`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqadd_u16`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqadd_u32`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqadd_u64`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqaddb_u8`neon`
  Unsigned saturating accumulate of signed value Arm’s documentation
vsqaddd_u64`neon`
  Unsigned saturating accumulate of signed value Arm’s documentation
vsqaddh_u16`neon`
  Unsigned saturating accumulate of signed value Arm’s documentation
vsqaddq_u8`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqaddq_u16`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqaddq_u32`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqaddq_u64`neon`
  Unsigned saturating Accumulate of Signed value. Arm’s documentation
vsqadds_u32`neon`
  Unsigned saturating accumulate of signed value Arm’s documentation
vsqrt_f16`fp16` and `neon`
  Calculates the square root of each lane. Arm’s documentation
vsqrt_f32`neon`
  Calculates the square root of each lane. Arm’s documentation
vsqrt_f64`neon`
  Calculates the square root of each lane. Arm’s documentation
vsqrtq_f16`fp16` and `neon`
  Calculates the square root of each lane. Arm’s documentation
vsqrtq_f32`neon`
  Calculates the square root of each lane. Arm’s documentation
vsqrtq_f64`neon`
  Calculates the square root of each lane. Arm’s documentation
vsra_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsra_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsra_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsra_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsra_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsra_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsra_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsra_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsrad_n_s64`neon`
  Signed shift right and accumulate
vsrad_n_u64`neon`
  Unsigned shift right and accumulate
vsraq_n_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsraq_n_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsraq_n_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsraq_n_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed shift right and accumulate Arm’s documentation
vsraq_n_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsraq_n_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsraq_n_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsraq_n_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned shift right and accumulate Arm’s documentation
vsri_n_p8`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_p16`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_p64`aes` and `neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_s8`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_s16`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_s32`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_s64`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_u8`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_u16`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_u32`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsri_n_u64`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsrid_n_s64`neon`
  Shift right and insert Arm’s documentation
vsrid_n_u64`neon`
  Shift right and insert Arm’s documentation
vsriq_n_p8`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_p16`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_p64`aes` and `neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_s8`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_s16`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_s32`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_s64`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_u8`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_u16`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_u32`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vsriq_n_u64`neon`
  Shift Right and Insert (immediate) Arm’s documentation
vst1_f32⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_f64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_f32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f64_x2⚠`neon`
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f64_x3⚠`neon`
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f64_x4⚠`neon`
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_f64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_lane_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_p8⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_p8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p16⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_p64⚠`aes` and `neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_p16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p64_x2⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p64_x3⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_p64_x4⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_s8⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_s8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s16⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_s32⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_s64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_s16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_s64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1_u8⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_u8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u16⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_u32⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_u64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_u16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_u64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f32⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_f64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_f32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f64_x2⚠`neon`
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f64_x3⚠`neon`
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f64_x4⚠`neon`
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_f64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_lane_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_p8⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_p8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p16⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_p64⚠`aes` and `neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_p16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p64_x2⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p64_x3⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_p64_x4⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_s8⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_s8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s16⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_s32⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_s64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_s16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_s64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_u8⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_u8_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u8_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u8_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u16⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_u32⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_u64⚠`neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_u16_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u16_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u16_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u32_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u32_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u32_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u64_x2⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u64_x3⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_u64_x4⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst2_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_f64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_f64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_p64⚠`aes` and `neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_s64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_u64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_f64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_f64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_p8⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_p64⚠`aes` and `neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_s8⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_s64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_u8⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_u64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_p64⚠`aes` and `neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_s64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_u64⚠`neon`
  Store multiple 2-element structures from two registers Arm’s documentation
vst3_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_f64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_f64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_p64⚠`aes` and `neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_s64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_u64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_f64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_f64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_p8⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_p64⚠`aes` and `neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_s8⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_s64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_u8⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_u64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_p64⚠`aes` and `neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_s64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_u64⚠`neon`
  Store multiple 3-element structures from three registers Arm’s documentation
vst4_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_f64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_f64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_p64⚠`aes` and `neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_s64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_u64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_p64⚠`aes` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_s64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_u64⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_f64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_f32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_f64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_p8⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_p64⚠`aes` and `neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_s8⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_s64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_u8⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_u64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_p8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_p16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_p64⚠`aes` and `neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_s8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_s16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_s32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_s64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_u8⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_u16⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_u32⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_u64⚠`neon`
  Store multiple 4-element structures from four registers Arm’s documentation
vstrq_p128⚠`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Store SIMD&FP register (immediate offset) Arm’s documentation
vsub_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Subtract Arm’s documentation
vsub_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_f64`neon`
  Subtract Arm’s documentation
vsub_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsub_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubd_s64`neon`
  Subtract Arm’s documentation
vsubd_u64`neon`
  Subtract Arm’s documentation
vsubhn_high_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_high_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_high_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_high_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_high_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_high_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubhn_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract returning high narrow Arm’s documentation
vsubl_high_s8`neon`
  Signed Subtract Long Arm’s documentation
vsubl_high_s16`neon`
  Signed Subtract Long Arm’s documentation
vsubl_high_s32`neon`
  Signed Subtract Long Arm’s documentation
vsubl_high_u8`neon`
  Unsigned Subtract Long Arm’s documentation
vsubl_high_u16`neon`
  Unsigned Subtract Long Arm’s documentation
vsubl_high_u32`neon`
  Unsigned Subtract Long Arm’s documentation
vsubl_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Subtract Long Arm’s documentation
vsubl_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Subtract Long Arm’s documentation
vsubl_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Subtract Long Arm’s documentation
vsubl_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Subtract Long Arm’s documentation
vsubl_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Subtract Long Arm’s documentation
vsubl_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Subtract Long Arm’s documentation
vsubq_f16`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Subtract Arm’s documentation
vsubq_f32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_f64`neon`
  Subtract Arm’s documentation
vsubq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_s64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubq_u64`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Subtract Arm’s documentation
vsubw_high_s8`neon`
  Signed Subtract Wide Arm’s documentation
vsubw_high_s16`neon`
  Signed Subtract Wide Arm’s documentation
vsubw_high_s32`neon`
  Signed Subtract Wide Arm’s documentation
vsubw_high_u8`neon`
  Unsigned Subtract Wide Arm’s documentation
vsubw_high_u16`neon`
  Unsigned Subtract Wide Arm’s documentation
vsubw_high_u32`neon`
  Unsigned Subtract Wide Arm’s documentation
vsubw_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Subtract Wide Arm’s documentation
vsubw_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Subtract Wide Arm’s documentation
vsubw_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed Subtract Wide Arm’s documentation
vsubw_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Subtract Wide Arm’s documentation
vsubw_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Subtract Wide Arm’s documentation
vsubw_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned Subtract Wide Arm’s documentation
vtbl1_p8`neon`
  Table look-up Arm’s documentation
vtbl1_s8`neon`
  Table look-up Arm’s documentation
vtbl1_u8`neon`
  Table look-up Arm’s documentation
vtbl2_p8`neon`
  Table look-up Arm’s documentation
vtbl2_s8`neon`
  Table look-up Arm’s documentation
vtbl2_u8`neon`
  Table look-up Arm’s documentation
vtbl3_p8`neon`
  Table look-up Arm’s documentation
vtbl3_s8`neon`
  Table look-up Arm’s documentation
vtbl3_u8`neon`
  Table look-up Arm’s documentation
vtbl4_p8`neon`
  Table look-up Arm’s documentation
vtbl4_s8`neon`
  Table look-up Arm’s documentation
vtbl4_u8`neon`
  Table look-up Arm’s documentation
vtbx1_p8`neon`
  Extended table look-up Arm’s documentation
vtbx1_s8`neon`
  Extended table look-up Arm’s documentation
vtbx1_u8`neon`
  Extended table look-up Arm’s documentation
vtbx2_p8`neon`
  Extended table look-up Arm’s documentation
vtbx2_s8`neon`
  Extended table look-up Arm’s documentation
vtbx2_u8`neon`
  Extended table look-up Arm’s documentation
vtbx3_p8`neon`
  Extended table look-up Arm’s documentation
vtbx3_s8`neon`
  Extended table look-up Arm’s documentation
vtbx3_u8`neon`
  Extended table look-up Arm’s documentation
vtbx4_p8`neon`
  Extended table look-up Arm’s documentation
vtbx4_s8`neon`
  Extended table look-up Arm’s documentation
vtbx4_u8`neon`
  Extended table look-up Arm’s documentation
vtrn1_f16`fp16` and `neon`
  Transpose vectors Arm’s documentation
vtrn1_f32`neon`
  Transpose vectors Arm’s documentation
vtrn1_p8`neon`
  Transpose vectors Arm’s documentation
vtrn1_p16`neon`
  Transpose vectors Arm’s documentation
vtrn1_s8`neon`
  Transpose vectors Arm’s documentation
vtrn1_s16`neon`
  Transpose vectors Arm’s documentation
vtrn1_s32`neon`
  Transpose vectors Arm’s documentation
vtrn1_u8`neon`
  Transpose vectors Arm’s documentation
vtrn1_u16`neon`
  Transpose vectors Arm’s documentation
vtrn1_u32`neon`
  Transpose vectors Arm’s documentation
vtrn1q_f16`fp16` and `neon`
  Transpose vectors Arm’s documentation
vtrn1q_f32`neon`
  Transpose vectors Arm’s documentation
vtrn1q_f64`neon`
  Transpose vectors Arm’s documentation
vtrn1q_p8`neon`
  Transpose vectors Arm’s documentation
vtrn1q_p16`neon`
  Transpose vectors Arm’s documentation
vtrn1q_p64`neon`
  Transpose vectors Arm’s documentation
vtrn1q_s8`neon`
  Transpose vectors Arm’s documentation
vtrn1q_s16`neon`
  Transpose vectors Arm’s documentation
vtrn1q_s32`neon`
  Transpose vectors Arm’s documentation
vtrn1q_s64`neon`
  Transpose vectors Arm’s documentation
vtrn1q_u8`neon`
  Transpose vectors Arm’s documentation
vtrn1q_u16`neon`
  Transpose vectors Arm’s documentation
vtrn1q_u32`neon`
  Transpose vectors Arm’s documentation
vtrn1q_u64`neon`
  Transpose vectors Arm’s documentation
vtrn2_f16`fp16` and `neon`
  Transpose vectors Arm’s documentation
vtrn2_f32`neon`
  Transpose vectors Arm’s documentation
vtrn2_p8`neon`
  Transpose vectors Arm’s documentation
vtrn2_p16`neon`
  Transpose vectors Arm’s documentation
vtrn2_s8`neon`
  Transpose vectors Arm’s documentation
vtrn2_s16`neon`
  Transpose vectors Arm’s documentation
vtrn2_s32`neon`
  Transpose vectors Arm’s documentation
vtrn2_u8`neon`
  Transpose vectors Arm’s documentation
vtrn2_u16`neon`
  Transpose vectors Arm’s documentation
vtrn2_u32`neon`
  Transpose vectors Arm’s documentation
vtrn2q_f16`fp16` and `neon`
  Transpose vectors Arm’s documentation
vtrn2q_f32`neon`
  Transpose vectors Arm’s documentation
vtrn2q_f64`neon`
  Transpose vectors Arm’s documentation
vtrn2q_p8`neon`
  Transpose vectors Arm’s documentation
vtrn2q_p16`neon`
  Transpose vectors Arm’s documentation
vtrn2q_p64`neon`
  Transpose vectors Arm’s documentation
vtrn2q_s8`neon`
  Transpose vectors Arm’s documentation
vtrn2q_s16`neon`
  Transpose vectors Arm’s documentation
vtrn2q_s32`neon`
  Transpose vectors Arm’s documentation
vtrn2q_s64`neon`
  Transpose vectors Arm’s documentation
vtrn2q_u8`neon`
  Transpose vectors Arm’s documentation
vtrn2q_u16`neon`
  Transpose vectors Arm’s documentation
vtrn2q_u32`neon`
  Transpose vectors Arm’s documentation
vtrn2q_u64`neon`
  Transpose vectors Arm’s documentation
vtrn_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Transpose elements Arm’s documentation
vtrn_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrn_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Transpose elements Arm’s documentation
vtrnq_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtrnq_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Transpose elements Arm’s documentation
vtst_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_p64`neon`
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_s64`neon`
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtst_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtst_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtst_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtst_u64`neon`
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtstd_s64`neon`
  Compare bitwise test bits nonzero Arm’s documentation
vtstd_u64`neon`
  Compare bitwise test bits nonzero Arm’s documentation
vtstq_p8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_p16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_p64`neon`
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_s8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_s16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_s32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_s64`neon`
  Signed compare bitwise Test bits nonzero Arm’s documentation
vtstq_u8`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtstq_u16`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtstq_u32`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vtstq_u64`neon`
  Unsigned compare bitwise Test bits nonzero Arm’s documentation
vuqadd_s8`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqadd_s16`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqadd_s32`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqadd_s64`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqaddb_s8`neon`
  Signed saturating accumulate of unsigned value Arm’s documentation
vuqaddd_s64`neon`
  Signed saturating accumulate of unsigned value Arm’s documentation
vuqaddh_s16`neon`
  Signed saturating accumulate of unsigned value Arm’s documentation
vuqaddq_s8`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqaddq_s16`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqaddq_s32`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqaddq_s64`neon`
  Signed saturating Accumulate of Unsigned value. Arm’s documentation
vuqadds_s32`neon`
  Signed saturating accumulate of unsigned value Arm’s documentation
vuzp1_f16`fp16` and `neon`
  Unzip vectors Arm’s documentation
vuzp1_f32`neon`
  Unzip vectors Arm’s documentation
vuzp1_p8`neon`
  Unzip vectors Arm’s documentation
vuzp1_p16`neon`
  Unzip vectors Arm’s documentation
vuzp1_s8`neon`
  Unzip vectors Arm’s documentation
vuzp1_s16`neon`
  Unzip vectors Arm’s documentation
vuzp1_s32`neon`
  Unzip vectors Arm’s documentation
vuzp1_u8`neon`
  Unzip vectors Arm’s documentation
vuzp1_u16`neon`
  Unzip vectors Arm’s documentation
vuzp1_u32`neon`
  Unzip vectors Arm’s documentation
vuzp1q_f16`fp16` and `neon`
  Unzip vectors Arm’s documentation
vuzp1q_f32`neon`
  Unzip vectors Arm’s documentation
vuzp1q_f64`neon`
  Unzip vectors Arm’s documentation
vuzp1q_p8`neon`
  Unzip vectors Arm’s documentation
vuzp1q_p16`neon`
  Unzip vectors Arm’s documentation
vuzp1q_p64`neon`
  Unzip vectors Arm’s documentation
vuzp1q_s8`neon`
  Unzip vectors Arm’s documentation
vuzp1q_s16`neon`
  Unzip vectors Arm’s documentation
vuzp1q_s32`neon`
  Unzip vectors Arm’s documentation
vuzp1q_s64`neon`
  Unzip vectors Arm’s documentation
vuzp1q_u8`neon`
  Unzip vectors Arm’s documentation
vuzp1q_u16`neon`
  Unzip vectors Arm’s documentation
vuzp1q_u32`neon`
  Unzip vectors Arm’s documentation
vuzp1q_u64`neon`
  Unzip vectors Arm’s documentation
vuzp2_f16`fp16` and `neon`
  Unzip vectors Arm’s documentation
vuzp2_f32`neon`
  Unzip vectors Arm’s documentation
vuzp2_p8`neon`
  Unzip vectors Arm’s documentation
vuzp2_p16`neon`
  Unzip vectors Arm’s documentation
vuzp2_s8`neon`
  Unzip vectors Arm’s documentation
vuzp2_s16`neon`
  Unzip vectors Arm’s documentation
vuzp2_s32`neon`
  Unzip vectors Arm’s documentation
vuzp2_u8`neon`
  Unzip vectors Arm’s documentation
vuzp2_u16`neon`
  Unzip vectors Arm’s documentation
vuzp2_u32`neon`
  Unzip vectors Arm’s documentation
vuzp2q_f16`fp16` and `neon`
  Unzip vectors Arm’s documentation
vuzp2q_f32`neon`
  Unzip vectors Arm’s documentation
vuzp2q_f64`neon`
  Unzip vectors Arm’s documentation
vuzp2q_p8`neon`
  Unzip vectors Arm’s documentation
vuzp2q_p16`neon`
  Unzip vectors Arm’s documentation
vuzp2q_p64`neon`
  Unzip vectors Arm’s documentation
vuzp2q_s8`neon`
  Unzip vectors Arm’s documentation
vuzp2q_s16`neon`
  Unzip vectors Arm’s documentation
vuzp2q_s32`neon`
  Unzip vectors Arm’s documentation
vuzp2q_s64`neon`
  Unzip vectors Arm’s documentation
vuzp2q_u8`neon`
  Unzip vectors Arm’s documentation
vuzp2q_u16`neon`
  Unzip vectors Arm’s documentation
vuzp2q_u32`neon`
  Unzip vectors Arm’s documentation
vuzp2q_u64`neon`
  Unzip vectors Arm’s documentation
vuzp_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Unzip vectors Arm’s documentation
vuzp_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzp_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Unzip vectors Arm’s documentation
vuzpq_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vuzpq_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unzip vectors Arm’s documentation
vxarq_u64`neon` and `sha3`
  Exclusive OR and rotate Arm’s documentation
vzip1_f16`fp16` and `neon`
  Zip vectors Arm’s documentation
vzip1_f32`neon`
  Zip vectors Arm’s documentation
vzip1_p8`neon`
  Zip vectors Arm’s documentation
vzip1_p16`neon`
  Zip vectors Arm’s documentation
vzip1_s8`neon`
  Zip vectors Arm’s documentation
vzip1_s16`neon`
  Zip vectors Arm’s documentation
vzip1_s32`neon`
  Zip vectors Arm’s documentation
vzip1_u8`neon`
  Zip vectors Arm’s documentation
vzip1_u16`neon`
  Zip vectors Arm’s documentation
vzip1_u32`neon`
  Zip vectors Arm’s documentation
vzip1q_f16`fp16` and `neon`
  Zip vectors Arm’s documentation
vzip1q_f32`neon`
  Zip vectors Arm’s documentation
vzip1q_f64`neon`
  Zip vectors Arm’s documentation
vzip1q_p8`neon`
  Zip vectors Arm’s documentation
vzip1q_p16`neon`
  Zip vectors Arm’s documentation
vzip1q_p64`neon`
  Zip vectors Arm’s documentation
vzip1q_s8`neon`
  Zip vectors Arm’s documentation
vzip1q_s16`neon`
  Zip vectors Arm’s documentation
vzip1q_s32`neon`
  Zip vectors Arm’s documentation
vzip1q_s64`neon`
  Zip vectors Arm’s documentation
vzip1q_u8`neon`
  Zip vectors Arm’s documentation
vzip1q_u16`neon`
  Zip vectors Arm’s documentation
vzip1q_u32`neon`
  Zip vectors Arm’s documentation
vzip1q_u64`neon`
  Zip vectors Arm’s documentation
vzip2_f16`fp16` and `neon`
  Zip vectors Arm’s documentation
vzip2_f32`neon`
  Zip vectors Arm’s documentation
vzip2_p8`neon`
  Zip vectors Arm’s documentation
vzip2_p16`neon`
  Zip vectors Arm’s documentation
vzip2_s8`neon`
  Zip vectors Arm’s documentation
vzip2_s16`neon`
  Zip vectors Arm’s documentation
vzip2_s32`neon`
  Zip vectors Arm’s documentation
vzip2_u8`neon`
  Zip vectors Arm’s documentation
vzip2_u16`neon`
  Zip vectors Arm’s documentation
vzip2_u32`neon`
  Zip vectors Arm’s documentation
vzip2q_f16`fp16` and `neon`
  Zip vectors Arm’s documentation
vzip2q_f32`neon`
  Zip vectors Arm’s documentation
vzip2q_f64`neon`
  Zip vectors Arm’s documentation
vzip2q_p8`neon`
  Zip vectors Arm’s documentation
vzip2q_p16`neon`
  Zip vectors Arm’s documentation
vzip2q_p64`neon`
  Zip vectors Arm’s documentation
vzip2q_s8`neon`
  Zip vectors Arm’s documentation
vzip2q_s16`neon`
  Zip vectors Arm’s documentation
vzip2q_s32`neon`
  Zip vectors Arm’s documentation
vzip2q_s64`neon`
  Zip vectors Arm’s documentation
vzip2q_u8`neon`
  Zip vectors Arm’s documentation
vzip2q_u16`neon`
  Zip vectors Arm’s documentation
vzip2q_u32`neon`
  Zip vectors Arm’s documentation
vzip2q_u64`neon`
  Zip vectors Arm’s documentation
vzip_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Zip vectors Arm’s documentation
vzip_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzip_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_f16Little-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Zip vectors Arm’s documentation
vzipq_f32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_p8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_p16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_s8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_s16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_s32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_u8Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_u16Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
vzipq_u32Little-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Zip vectors Arm’s documentation
__arm_mte_create_random_tag⚠Experimental`mte`
  Return a pointer containing a randomly generated logical address tag.
__arm_mte_exclude_tag⚠Experimental`mte`
  Add a logical tag to the set of excluded logical tags.
__arm_mte_get_tag⚠Experimental`mte`
  Load an allocation tag from memory, returning a new pointer with the corresponding logical tag.
__arm_mte_increment_tag⚠Experimental`mte`
  Return a pointer with the logical address tag offset by a value.
__arm_mte_ptrdiff⚠Experimental`mte`
  Calculate the difference between the address parts of two pointers, ignoring the tags, and sign-extending the result.
__arm_mte_set_tag⚠Experimental`mte`
  Store an allocation tag for the 16-byte granule of memory.
__dmb⚠ExperimentalAArch64 or ARM or ARM64EC
  Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
__dsb⚠ExperimentalAArch64 or ARM or ARM64EC
  Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
__isb⚠ExperimentalAArch64 or ARM or ARM64EC
  Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
__nop⚠ExperimentalAArch64 or ARM or ARM64EC
  Generates an unspecified no-op instruction.
__rndr⚠Experimental`rand`
  Stores a 64-bit random number into the object pointed to by the argument and returns zero. If the implementation could not generate a random number within a reasonable period of time the object pointed to by the input is set to zero and a non-zero value is returned.
__rndrrs⚠Experimental`rand`
  Reseeds the random number generator. After that stores a 64-bit random number into the object pointed to by the argument and returns zero. If the implementation could not generate a random number within a reasonable period of time the object pointed to by the input is set to zero and a non-zero value is returned.
__sev⚠Experimental(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v6`)
  Generates a SEV (send a global event) hint instruction.
__sevl⚠Experimental(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v8`)
  Generates a send a local event hint instruction.
__wfe⚠Experimental(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v6`)
  Generates a WFE (wait for event) hint instruction, or nothing.
__wfi⚠Experimental(AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v6`)
  Generates a WFI (wait for interrupt) hint instruction, or nothing.
__yield⚠Experimental(AArch64 or ARM or ARM64EC) and (AArch64, or ARM64EC, or `v6t2`, or `v6k` and non-`thumb-mode`, or `mclass` and `v6`)
  Generates a YIELD hint instruction.
_prefetch⚠Experimental
  Fetch the cache line that contains address `p` using the given `RW` and `LOCALITY`.
svaba_n_s8Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_s16Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_s32Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_s64Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_u8Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_u16Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_u32Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_n_u64Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_s8Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_s16Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_s32Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_s64Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_u8Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_u16Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_u32Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svaba_u64Experimental`sve2` and `sve`
  Absolute difference and accumulate Arm’s documentation
svabalb_n_s16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_n_s32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_n_s64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_n_u16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_n_u32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_n_u64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_s16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_s32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_s64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_u16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_u32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalb_u64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabalt_n_s16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_n_s32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_n_s64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_n_u16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_n_u32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_n_u64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_s16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_s32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_s64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_u16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_u32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabalt_u64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabd_f32_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_f32_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_f32_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_f64_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_f64_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_f64_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_f32_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_f32_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_f32_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_f64_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_f64_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_f64_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s8_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s8_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s8_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s16_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s16_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s16_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s32_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s32_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s32_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s64_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s64_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_s64_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u8_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u8_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u8_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u16_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u16_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u16_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u32_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u32_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u32_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u64_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u64_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_n_u64_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s8_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s8_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s8_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s16_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s16_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s16_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s32_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s32_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s32_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s64_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s64_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_s64_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u8_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u8_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u8_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u16_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u16_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u16_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u32_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u32_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u32_zExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u64_mExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u64_xExperimental`sve`
  Absolute difference Arm’s documentation
svabd_u64_zExperimental`sve`
  Absolute difference Arm’s documentation
svabdlb_n_s16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_n_s32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_n_s64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_n_u16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_n_u32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_n_u64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_s16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_s32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_s64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_u16Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_u32Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlb_u64Experimental`sve2` and `sve`
  Absolute difference long (bottom) Arm’s documentation
svabdlt_n_s16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_n_s32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_n_s64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_n_u16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_n_u32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_n_u64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_s16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_s32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_s64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_u16Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_u32Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabdlt_u64Experimental`sve2` and `sve`
  Absolute difference long (top) Arm’s documentation
svabs_f32_mExperimental`sve`
  Absolute value Arm’s documentation
svabs_f32_xExperimental`sve`
  Absolute value Arm’s documentation
svabs_f32_zExperimental`sve`
  Absolute value Arm’s documentation
svabs_f64_mExperimental`sve`
  Absolute value Arm’s documentation
svabs_f64_xExperimental`sve`
  Absolute value Arm’s documentation
svabs_f64_zExperimental`sve`
  Absolute value Arm’s documentation
svabs_s8_mExperimental`sve`
  Absolute value Arm’s documentation
svabs_s8_xExperimental`sve`
  Absolute value Arm’s documentation
svabs_s8_zExperimental`sve`
  Absolute value Arm’s documentation
svabs_s16_mExperimental`sve`
  Absolute value Arm’s documentation
svabs_s16_xExperimental`sve`
  Absolute value Arm’s documentation
svabs_s16_zExperimental`sve`
  Absolute value Arm’s documentation
svabs_s32_mExperimental`sve`
  Absolute value Arm’s documentation
svabs_s32_xExperimental`sve`
  Absolute value Arm’s documentation
svabs_s32_zExperimental`sve`
  Absolute value Arm’s documentation
svabs_s64_mExperimental`sve`
  Absolute value Arm’s documentation
svabs_s64_xExperimental`sve`
  Absolute value Arm’s documentation
svabs_s64_zExperimental`sve`
  Absolute value Arm’s documentation
svacge_f32Experimental`sve`
  Absolute compare greater than or equal to Arm’s documentation
svacge_f64Experimental`sve`
  Absolute compare greater than or equal to Arm’s documentation
svacge_n_f32Experimental`sve`
  Absolute compare greater than or equal to Arm’s documentation
svacge_n_f64Experimental`sve`
  Absolute compare greater than or equal to Arm’s documentation
svacgt_f32Experimental`sve`
  Absolute compare greater than Arm’s documentation
svacgt_f64Experimental`sve`
  Absolute compare greater than Arm’s documentation
svacgt_n_f32Experimental`sve`
  Absolute compare greater than Arm’s documentation
svacgt_n_f64Experimental`sve`
  Absolute compare greater than Arm’s documentation
svacle_f32Experimental`sve`
  Absolute compare less than or equal to Arm’s documentation
svacle_f64Experimental`sve`
  Absolute compare less than or equal to Arm’s documentation
svacle_n_f32Experimental`sve`
  Absolute compare less than or equal to Arm’s documentation
svacle_n_f64Experimental`sve`
  Absolute compare less than or equal to Arm’s documentation
svaclt_f32Experimental`sve`
  Absolute compare less than Arm’s documentation
svaclt_f64Experimental`sve`
  Absolute compare less than Arm’s documentation
svaclt_n_f32Experimental`sve`
  Absolute compare less than Arm’s documentation
svaclt_n_f64Experimental`sve`
  Absolute compare less than Arm’s documentation
svadalp_s16_mExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s16_xExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s16_zExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s32_mExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s32_xExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s32_zExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s64_mExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s64_xExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_s64_zExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u16_mExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u16_xExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u16_zExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u32_mExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u32_xExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u32_zExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u64_mExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u64_xExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadalp_u64_zExperimental`sve2` and `sve`
  Add and accumulate long pairwise Arm’s documentation
svadclb_n_u32Experimental`sve2` and `sve`
  Add with carry long (bottom) Arm’s documentation
svadclb_n_u64Experimental`sve2` and `sve`
  Add with carry long (bottom) Arm’s documentation
svadclb_u32Experimental`sve2` and `sve`
  Add with carry long (bottom) Arm’s documentation
svadclb_u64Experimental`sve2` and `sve`
  Add with carry long (bottom) Arm’s documentation
svadclt_n_u32Experimental`sve2` and `sve`
  Add with carry long (top) Arm’s documentation
svadclt_n_u64Experimental`sve2` and `sve`
  Add with carry long (top) Arm’s documentation
svadclt_u32Experimental`sve2` and `sve`
  Add with carry long (top) Arm’s documentation
svadclt_u64Experimental`sve2` and `sve`
  Add with carry long (top) Arm’s documentation
svadd_f32_mExperimental`sve`
  Add Arm’s documentation
svadd_f32_xExperimental`sve`
  Add Arm’s documentation
svadd_f32_zExperimental`sve`
  Add Arm’s documentation
svadd_f64_mExperimental`sve`
  Add Arm’s documentation
svadd_f64_xExperimental`sve`
  Add Arm’s documentation
svadd_f64_zExperimental`sve`
  Add Arm’s documentation
svadd_n_f32_mExperimental`sve`
  Add Arm’s documentation
svadd_n_f32_xExperimental`sve`
  Add Arm’s documentation
svadd_n_f32_zExperimental`sve`
  Add Arm’s documentation
svadd_n_f64_mExperimental`sve`
  Add Arm’s documentation
svadd_n_f64_xExperimental`sve`
  Add Arm’s documentation
svadd_n_f64_zExperimental`sve`
  Add Arm’s documentation
svadd_n_s8_mExperimental`sve`
  Add Arm’s documentation
svadd_n_s8_xExperimental`sve`
  Add Arm’s documentation
svadd_n_s8_zExperimental`sve`
  Add Arm’s documentation
svadd_n_s16_mExperimental`sve`
  Add Arm’s documentation
svadd_n_s16_xExperimental`sve`
  Add Arm’s documentation
svadd_n_s16_zExperimental`sve`
  Add Arm’s documentation
svadd_n_s32_mExperimental`sve`
  Add Arm’s documentation
svadd_n_s32_xExperimental`sve`
  Add Arm’s documentation
svadd_n_s32_zExperimental`sve`
  Add Arm’s documentation
svadd_n_s64_mExperimental`sve`
  Add Arm’s documentation
svadd_n_s64_xExperimental`sve`
  Add Arm’s documentation
svadd_n_s64_zExperimental`sve`
  Add Arm’s documentation
svadd_n_u8_mExperimental`sve`
  Add Arm’s documentation
svadd_n_u8_xExperimental`sve`
  Add Arm’s documentation
svadd_n_u8_zExperimental`sve`
  Add Arm’s documentation
svadd_n_u16_mExperimental`sve`
  Add Arm’s documentation
svadd_n_u16_xExperimental`sve`
  Add Arm’s documentation
svadd_n_u16_zExperimental`sve`
  Add Arm’s documentation
svadd_n_u32_mExperimental`sve`
  Add Arm’s documentation
svadd_n_u32_xExperimental`sve`
  Add Arm’s documentation
svadd_n_u32_zExperimental`sve`
  Add Arm’s documentation
svadd_n_u64_mExperimental`sve`
  Add Arm’s documentation
svadd_n_u64_xExperimental`sve`
  Add Arm’s documentation
svadd_n_u64_zExperimental`sve`
  Add Arm’s documentation
svadd_s8_mExperimental`sve`
  Add Arm’s documentation
svadd_s8_xExperimental`sve`
  Add Arm’s documentation
svadd_s8_zExperimental`sve`
  Add Arm’s documentation
svadd_s16_mExperimental`sve`
  Add Arm’s documentation
svadd_s16_xExperimental`sve`
  Add Arm’s documentation
svadd_s16_zExperimental`sve`
  Add Arm’s documentation
svadd_s32_mExperimental`sve`
  Add Arm’s documentation
svadd_s32_xExperimental`sve`
  Add Arm’s documentation
svadd_s32_zExperimental`sve`
  Add Arm’s documentation
svadd_s64_mExperimental`sve`
  Add Arm’s documentation
svadd_s64_xExperimental`sve`
  Add Arm’s documentation
svadd_s64_zExperimental`sve`
  Add Arm’s documentation
svadd_u8_mExperimental`sve`
  Add Arm’s documentation
svadd_u8_xExperimental`sve`
  Add Arm’s documentation
svadd_u8_zExperimental`sve`
  Add Arm’s documentation
svadd_u16_mExperimental`sve`
  Add Arm’s documentation
svadd_u16_xExperimental`sve`
  Add Arm’s documentation
svadd_u16_zExperimental`sve`
  Add Arm’s documentation
svadd_u32_mExperimental`sve`
  Add Arm’s documentation
svadd_u32_xExperimental`sve`
  Add Arm’s documentation
svadd_u32_zExperimental`sve`
  Add Arm’s documentation
svadd_u64_mExperimental`sve`
  Add Arm’s documentation
svadd_u64_xExperimental`sve`
  Add Arm’s documentation
svadd_u64_zExperimental`sve`
  Add Arm’s documentation
svadda_f32Experimental`sve`
  Add reduction (strictly-ordered) Arm’s documentation
svadda_f64Experimental`sve`
  Add reduction (strictly-ordered) Arm’s documentation
svaddhnb_n_s16Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_n_s32Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_n_s64Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_n_u16Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_n_u32Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_n_u64Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_s16Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_s32Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_s64Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_u16Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_u32Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnb_u64Experimental`sve2` and `sve`
  Add narrow high part (bottom) Arm’s documentation
svaddhnt_n_s16Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_n_s32Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_n_s64Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_n_u16Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_n_u32Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_n_u64Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_s16Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_s32Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_s64Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_u16Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_u32Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddhnt_u64Experimental`sve2` and `sve`
  Add narrow high part (top) Arm’s documentation
svaddlb_n_s16Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_n_s32Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_n_s64Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_n_u16Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_n_u32Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_n_u64Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_s16Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_s32Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_s64Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_u16Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_u32Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlb_u64Experimental`sve2` and `sve`
  Add long (bottom) Arm’s documentation
svaddlbt_n_s16Experimental`sve2` and `sve`
  Add long (bottom + top) Arm’s documentation
svaddlbt_n_s32Experimental`sve2` and `sve`
  Add long (bottom + top) Arm’s documentation
svaddlbt_n_s64Experimental`sve2` and `sve`
  Add long (bottom + top) Arm’s documentation
svaddlbt_s16Experimental`sve2` and `sve`
  Add long (bottom + top) Arm’s documentation
svaddlbt_s32Experimental`sve2` and `sve`
  Add long (bottom + top) Arm’s documentation
svaddlbt_s64Experimental`sve2` and `sve`
  Add long (bottom + top) Arm’s documentation
svaddlt_n_s16Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_n_s32Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_n_s64Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_n_u16Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_n_u32Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_n_u64Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_s16Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_s32Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_s64Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_u16Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_u32Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddlt_u64Experimental`sve2` and `sve`
  Add long (top) Arm’s documentation
svaddp_f32_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_f32_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_f64_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_f64_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s8_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s8_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s16_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s16_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s32_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s32_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s64_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_s64_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u8_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u8_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u16_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u16_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u32_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u32_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u64_mExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddp_u64_xExperimental`sve2` and `sve`
  Add pairwise Arm’s documentation
svaddv_f32Experimental`sve`
  Add reduction Arm’s documentation
svaddv_f64Experimental`sve`
  Add reduction Arm’s documentation
svaddv_s8Experimental`sve`
  Add reduction Arm’s documentation
svaddv_s16Experimental`sve`
  Add reduction Arm’s documentation
svaddv_s32Experimental`sve`
  Add reduction Arm’s documentation
svaddv_s64Experimental`sve`
  Add reduction Arm’s documentation
svaddv_u8Experimental`sve`
  Add reduction Arm’s documentation
svaddv_u16Experimental`sve`
  Add reduction Arm’s documentation
svaddv_u32Experimental`sve`
  Add reduction Arm’s documentation
svaddv_u64Experimental`sve`
  Add reduction Arm’s documentation
svaddwb_n_s16Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_n_s32Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_n_s64Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_n_u16Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_n_u32Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_n_u64Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_s16Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_s32Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_s64Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_u16Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_u32Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwb_u64Experimental`sve2` and `sve`
  Add wide (bottom) Arm’s documentation
svaddwt_n_s16Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_n_s32Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_n_s64Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_n_u16Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_n_u32Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_n_u64Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_s16Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_s32Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_s64Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_u16Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_u32Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svaddwt_u64Experimental`sve2` and `sve`
  Add wide (top) Arm’s documentation
svadrb_u32base_s32offsetExperimental`sve`
  Compute vector addresses for 8-bit data Arm’s documentation
svadrb_u32base_u32offsetExperimental`sve`
  Compute vector addresses for 8-bit data Arm’s documentation
svadrb_u64base_s64offsetExperimental`sve`
  Compute vector addresses for 8-bit data Arm’s documentation
svadrb_u64base_u64offsetExperimental`sve`
  Compute vector addresses for 8-bit data Arm’s documentation
svadrd_u32base_s32indexExperimental`sve`
  Compute vector addresses for 64-bit data Arm’s documentation
svadrd_u32base_u32indexExperimental`sve`
  Compute vector addresses for 64-bit data Arm’s documentation
svadrd_u64base_s64indexExperimental`sve`
  Compute vector addresses for 64-bit data Arm’s documentation
svadrd_u64base_u64indexExperimental`sve`
  Compute vector addresses for 64-bit data Arm’s documentation
svadrh_u32base_s32indexExperimental`sve`
  Compute vector addresses for 16-bit data Arm’s documentation
svadrh_u32base_u32indexExperimental`sve`
  Compute vector addresses for 16-bit data Arm’s documentation
svadrh_u64base_s64indexExperimental`sve`
  Compute vector addresses for 16-bit data Arm’s documentation
svadrh_u64base_u64indexExperimental`sve`
  Compute vector addresses for 16-bit data Arm’s documentation
svadrw_u32base_s32indexExperimental`sve`
  Compute vector addresses for 32-bit data Arm’s documentation
svadrw_u32base_u32indexExperimental`sve`
  Compute vector addresses for 32-bit data Arm’s documentation
svadrw_u64base_s64indexExperimental`sve`
  Compute vector addresses for 32-bit data Arm’s documentation
svadrw_u64base_u64indexExperimental`sve`
  Compute vector addresses for 32-bit data Arm’s documentation
svaesd_u8Experimental`sve2-aes` and `sve2` and `sve`
  AES single round decryption Arm’s documentation
svaese_u8Experimental`sve2-aes` and `sve2` and `sve`
  AES single round encryption Arm’s documentation
svaesimc_u8Experimental`sve2-aes` and `sve2` and `sve`
  AES inverse mix columns Arm’s documentation
svaesmc_u8Experimental`sve2-aes` and `sve2` and `sve`
  AES mix columns Arm’s documentation
svand_b_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s8_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s8_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s8_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s16_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s16_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s16_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s32_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s32_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s32_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s64_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s64_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_s64_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u8_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u8_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u8_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u16_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u16_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u16_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u32_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u32_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u32_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u64_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u64_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_n_u64_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s8_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s8_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s8_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s16_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s16_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s16_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s32_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s32_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s32_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s64_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s64_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_s64_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u8_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u8_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u8_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u16_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u16_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u16_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u32_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u32_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u32_zExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u64_mExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u64_xExperimental`sve`
  Bitwise AND Arm’s documentation
svand_u64_zExperimental`sve`
  Bitwise AND Arm’s documentation
svandv_s8Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_s16Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_s32Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_s64Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_u8Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_u16Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_u32Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svandv_u64Experimental`sve`
  Bitwise AND reduction to scalar Arm’s documentation
svasr_n_s8_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s8_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s8_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s16_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s16_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s16_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s32_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s32_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s32_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s64_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s64_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_n_s64_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s8_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s8_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s8_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s16_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s16_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s16_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s32_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s32_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s32_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s64_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s64_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_s64_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s8_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s8_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s8_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s16_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s16_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s16_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s32_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s32_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_n_s32_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s8_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s8_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s8_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s16_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s16_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s16_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s32_mExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s32_xExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasr_wide_s32_zExperimental`sve`
  Arithmetic shift right Arm’s documentation
svasrd_n_s8_mExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s8_xExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s8_zExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s16_mExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s16_xExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s16_zExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s32_mExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s32_xExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s32_zExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s64_mExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s64_xExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svasrd_n_s64_zExperimental`sve`
  Arithmetic shift right for divide by immediate Arm’s documentation
svbcax_n_s8Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_s16Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_s32Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_s64Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_u8Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_u16Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_u32Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_n_u64Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_s8Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_s16Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_s32Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_s64Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_u8Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_u16Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_u32Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbcax_u64Experimental`sve2` and `sve`
  Bitwise clear and exclusive OR Arm’s documentation
svbdep_n_u8Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_n_u16Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_n_u32Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_n_u64Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_u8Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_u16Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_u32Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbdep_u64Experimental`sve2-bitperm` and `sve2` and `sve`
  Scatter lower bits into positions selected by bitmask Arm’s documentation
svbext_n_u8Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_n_u16Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_n_u32Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_n_u64Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_u8Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_u16Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_u32Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbext_u64Experimental`sve2-bitperm` and `sve2` and `sve`
  Gather lower bits from positions selected by bitmask Arm’s documentation
svbgrp_n_u8Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_n_u16Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_n_u32Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_n_u64Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_u8Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_u16Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_u32Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbgrp_u64Experimental`sve2-bitperm` and `sve2` and `sve`
  Group bits to right or left as selected by bitmask Arm’s documentation
svbic_b_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s8_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s8_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s8_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s16_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s16_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s16_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s32_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s32_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s32_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s64_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s64_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_s64_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u8_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u8_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u8_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u16_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u16_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u16_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u32_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u32_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u32_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u64_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u64_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_n_u64_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s8_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s8_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s8_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s16_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s16_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s16_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s32_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s32_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s32_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s64_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s64_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_s64_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u8_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u8_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u8_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u16_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u16_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u16_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u32_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u32_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u32_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u64_mExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u64_xExperimental`sve`
  Bitwise clear Arm’s documentation
svbic_u64_zExperimental`sve`
  Bitwise clear Arm’s documentation
svbrka_b_mExperimental`sve`
  Break after first true condition Arm’s documentation
svbrka_b_zExperimental`sve`
  Break after first true condition Arm’s documentation
svbrkb_b_mExperimental`sve`
  Break before first true condition Arm’s documentation
svbrkb_b_zExperimental`sve`
  Break before first true condition Arm’s documentation
svbrkn_b_zExperimental`sve`
  Propagate break to next partition Arm’s documentation
svbrkpa_b_zExperimental`sve`
  Break after first true condition, propagating from previous partition Arm’s documentation
svbrkpb_b_zExperimental`sve`
  Break before first true condition, propagating from previous partition Arm’s documentation
svbsl1n_n_s8Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_s16Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_s32Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_s64Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_u8Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_u16Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_u32Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_n_u64Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_s8Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_s16Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_s32Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_s64Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_u8Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_u16Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_u32Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl1n_u64Experimental`sve2` and `sve`
  Bitwise select with first input inverted Arm’s documentation
svbsl2n_n_s8Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_s16Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_s32Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_s64Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_u8Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_u16Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_u32Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_n_u64Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_s8Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_s16Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_s32Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_s64Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_u8Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_u16Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_u32Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl2n_u64Experimental`sve2` and `sve`
  Bitwise select with second input inverted Arm’s documentation
svbsl_n_s8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_s16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_s32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_s64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_u8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_u16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_u32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_n_u64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_s8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_s16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_s32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_s64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_u8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_u16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_u32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svbsl_u64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svcadd_f32_mExperimental`sve`
  Complex add with rotate Arm’s documentation
svcadd_f32_xExperimental`sve`
  Complex add with rotate Arm’s documentation
svcadd_f32_zExperimental`sve`
  Complex add with rotate Arm’s documentation
svcadd_f64_mExperimental`sve`
  Complex add with rotate Arm’s documentation
svcadd_f64_xExperimental`sve`
  Complex add with rotate Arm’s documentation
svcadd_f64_zExperimental`sve`
  Complex add with rotate Arm’s documentation
svcadd_s8Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_s16Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_s32Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_s64Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_u8Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_u16Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_u32Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcadd_u64Experimental`sve2` and `sve`
  Complex add with rotate Arm’s documentation
svcdot_lane_s32Experimental`sve2` and `sve`
  Complex dot product Arm’s documentation
svcdot_lane_s64Experimental`sve2` and `sve`
  Complex dot product Arm’s documentation
svcdot_s32Experimental`sve2` and `sve`
  Complex dot product Arm’s documentation
svcdot_s64Experimental`sve2` and `sve`
  Complex dot product Arm’s documentation
svclasta_f32Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_f64Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_f32Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_f64Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_s8Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_s16Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_s32Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_s64Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_u8Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_u16Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_u32Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_n_u64Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_s8Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_s16Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_s32Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_s64Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_u8Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_u16Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_u32Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclasta_u64Experimental`sve`
  Conditionally extract element after last Arm’s documentation
svclastb_f32Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_f64Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_f32Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_f64Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_s8Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_s16Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_s32Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_s64Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_u8Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_u16Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_u32Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_n_u64Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_s8Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_s16Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_s32Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_s64Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_u8Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_u16Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_u32Experimental`sve`
  Conditionally extract last element Arm’s documentation
svclastb_u64Experimental`sve`
  Conditionally extract last element Arm’s documentation
svcls_s8_mExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s8_xExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s8_zExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s16_mExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s16_xExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s16_zExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s32_mExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s32_xExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s32_zExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s64_mExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s64_xExperimental`sve`
  Count leading sign bits Arm’s documentation
svcls_s64_zExperimental`sve`
  Count leading sign bits Arm’s documentation
svclz_s8_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s8_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s8_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s16_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s16_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s16_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s32_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s32_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s32_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s64_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s64_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_s64_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u8_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u8_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u8_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u16_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u16_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u16_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u32_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u32_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u32_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u64_mExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u64_xExperimental`sve`
  Count leading zero bits Arm’s documentation
svclz_u64_zExperimental`sve`
  Count leading zero bits Arm’s documentation
svcmla_f32_mExperimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_f32_xExperimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_f32_zExperimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_f64_mExperimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_f64_xExperimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_f64_zExperimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_lane_f32Experimental`sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_lane_s16Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_lane_s32Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_lane_u16Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_lane_u32Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_s8Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_s16Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_s32Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_s64Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_u8Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_u16Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_u32Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmla_u64Experimental`sve2` and `sve`
  Complex multiply-add with rotate Arm’s documentation
svcmpeq_f32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_f64Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_f32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_f64Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_s8Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_s16Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_s32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_s64Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_u8Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_u16Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_u32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_n_u64Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_s8Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_s16Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_s32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_s64Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_u8Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_u16Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_u32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_u64Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_wide_n_s8Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_wide_n_s16Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_wide_n_s32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_wide_s8Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_wide_s16Experimental`sve`
  Compare equal to Arm’s documentation
svcmpeq_wide_s32Experimental`sve`
  Compare equal to Arm’s documentation
svcmpge_f32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_f64Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_f32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_f64Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_s8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_s16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_s32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_s64Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_u8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_u16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_u32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_n_u64Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_s8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_s16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_s32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_s64Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_u8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_u16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_u32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_u64Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_n_s8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_n_s16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_n_s32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_n_u8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_n_u16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_n_u32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_s8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_s16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_s32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_u8Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_u16Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpge_wide_u32Experimental`sve`
  Compare greater than or equal to Arm’s documentation
svcmpgt_f32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_f64Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_f32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_f64Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_s8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_s16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_s32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_s64Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_u8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_u16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_u32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_n_u64Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_s8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_s16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_s32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_s64Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_u8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_u16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_u32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_u64Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_n_s8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_n_s16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_n_s32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_n_u8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_n_u16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_n_u32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_s8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_s16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_s32Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_u8Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_u16Experimental`sve`
  Compare greater than Arm’s documentation
svcmpgt_wide_u32Experimental`sve`
  Compare greater than Arm’s documentation
svcmple_f32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_f64Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_f32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_f64Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_s8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_s16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_s32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_s64Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_u8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_u16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_u32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_n_u64Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_s8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_s16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_s32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_s64Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_u8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_u16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_u32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_u64Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_n_s8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_n_s16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_n_s32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_n_u8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_n_u16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_n_u32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_s8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_s16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_s32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_u8Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_u16Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmple_wide_u32Experimental`sve`
  Compare less than or equal to Arm’s documentation
svcmplt_f32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_f64Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_f32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_f64Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_s8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_s16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_s32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_s64Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_u8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_u16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_u32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_n_u64Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_s8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_s16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_s32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_s64Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_u8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_u16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_u32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_u64Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_n_s8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_n_s16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_n_s32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_n_u8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_n_u16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_n_u32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_s8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_s16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_s32Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_u8Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_u16Experimental`sve`
  Compare less than Arm’s documentation
svcmplt_wide_u32Experimental`sve`
  Compare less than Arm’s documentation
svcmpne_f32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_f64Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_f32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_f64Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_s8Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_s16Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_s32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_s64Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_u8Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_u16Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_u32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_n_u64Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_s8Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_s16Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_s32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_s64Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_u8Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_u16Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_u32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_u64Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_wide_n_s8Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_wide_n_s16Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_wide_n_s32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_wide_s8Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_wide_s16Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpne_wide_s32Experimental`sve`
  Compare not equal to Arm’s documentation
svcmpuo_f32Experimental`sve`
  Compare unordered with Arm’s documentation
svcmpuo_f64Experimental`sve`
  Compare unordered with Arm’s documentation
svcmpuo_n_f32Experimental`sve`
  Compare unordered with Arm’s documentation
svcmpuo_n_f64Experimental`sve`
  Compare unordered with Arm’s documentation
svcnot_s8_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s8_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s8_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s16_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s16_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s16_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s32_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s32_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s32_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s64_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s64_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_s64_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u8_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u8_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u8_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u16_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u16_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u16_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u32_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u32_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u32_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u64_mExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u64_xExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnot_u64_zExperimental`sve`
  Logically invert boolean condition Arm’s documentation
svcnt_f32_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_f32_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_f32_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_f64_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_f64_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_f64_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s8_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s8_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s8_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s16_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s16_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s16_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s32_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s32_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s32_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s64_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s64_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_s64_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u8_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u8_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u8_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u16_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u16_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u16_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u32_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u32_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u32_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u64_mExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u64_xExperimental`sve`
  Count nonzero bits Arm’s documentation
svcnt_u64_zExperimental`sve`
  Count nonzero bits Arm’s documentation
svcntbExperimental`sve`
  Count the number of 8-bit elements in a vector Arm’s documentation
svcntb_patExperimental`sve`
  Count the number of 8-bit elements in a vector Arm’s documentation
svcntdExperimental`sve`
  Count the number of 64-bit elements in a vector Arm’s documentation
svcntd_patExperimental`sve`
  Count the number of 64-bit elements in a vector Arm’s documentation
svcnthExperimental`sve`
  Count the number of 16-bit elements in a vector Arm’s documentation
svcnth_patExperimental`sve`
  Count the number of 16-bit elements in a vector Arm’s documentation
svcntp_b8Experimental`sve`
  Count set predicate bits Arm’s documentation
svcntp_b16Experimental`sve`
  Count set predicate bits Arm’s documentation
svcntp_b32Experimental`sve`
  Count set predicate bits Arm’s documentation
svcntp_b64Experimental`sve`
  Count set predicate bits Arm’s documentation
svcntwExperimental`sve`
  Count the number of 32-bit elements in a vector Arm’s documentation
svcntw_patExperimental`sve`
  Count the number of 32-bit elements in a vector Arm’s documentation
svcompact_f32Experimental`sve`
  Shuffle active elements of vector to the right and fill with zero Arm’s documentation
svcompact_f64Experimental`sve`
  Shuffle active elements of vector to the right and fill with zero Arm’s documentation
svcompact_s32Experimental`sve`
  Shuffle active elements of vector to the right and fill with zero Arm’s documentation
svcompact_s64Experimental`sve`
  Shuffle active elements of vector to the right and fill with zero Arm’s documentation
svcompact_u32Experimental`sve`
  Shuffle active elements of vector to the right and fill with zero Arm’s documentation
svcompact_u64Experimental`sve`
  Shuffle active elements of vector to the right and fill with zero Arm’s documentation
svcreate2_f32Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_f64Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_s8Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_s16Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_s32Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_s64Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_u8Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_u16Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_u32Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate2_u64Experimental`sve`
  Create a tuple of two vectors Arm’s documentation
svcreate3_f32Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_f64Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_s8Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_s16Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_s32Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_s64Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_u8Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_u16Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_u32Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate3_u64Experimental`sve`
  Create a tuple of three vectors Arm’s documentation
svcreate4_f32Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_f64Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_s8Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_s16Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_s32Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_s64Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_u8Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_u16Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_u32Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcreate4_u64Experimental`sve`
  Create a tuple of four vectors Arm’s documentation
svcvt_f32_f64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_f64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_f64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_s32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_s32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_s32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_s64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_s64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_s64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_u32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_u32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_u32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_u64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_u64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f32_u64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_f32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_f32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_f32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_s32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_s32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_s32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_s64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_s64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_s64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_u32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_u32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_u32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_u64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_u64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_f64_u64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s32_f32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s32_f32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s32_f32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s32_f64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s32_f64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s32_f64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s64_f32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s64_f32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s64_f32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s64_f64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s64_f64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_s64_f64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u32_f32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u32_f32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u32_f32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u32_f64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u32_f64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u32_f64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u64_f32_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u64_f32_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u64_f32_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u64_f64_mExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u64_f64_xExperimental`sve`
  Floating-point convert Arm’s documentation
svcvt_u64_f64_zExperimental`sve`
  Floating-point convert Arm’s documentation
svcvtlt_f64_f32_mExperimental`sve2` and `sve`
  Up convert long (top) Arm’s documentation
svcvtlt_f64_f32_xExperimental`sve2` and `sve`
  Up convert long (top) Arm’s documentation
svcvtnt_f32_f64_mExperimental`sve2` and `sve`
  Down convert and narrow (top) Arm’s documentation
svcvtnt_f32_f64_xExperimental`sve2` and `sve`
  Down convert and narrow (top) Arm’s documentation
svcvtx_f32_f64_mExperimental`sve2` and `sve`
  Down convert, rounding to odd Arm’s documentation
svcvtx_f32_f64_xExperimental`sve2` and `sve`
  Down convert, rounding to odd Arm’s documentation
svcvtx_f32_f64_zExperimental`sve2` and `sve`
  Down convert, rounding to odd Arm’s documentation
svcvtxnt_f32_f64_mExperimental`sve2` and `sve`
  Down convert, rounding to odd (top) Arm’s documentation
svcvtxnt_f32_f64_xExperimental`sve2` and `sve`
  Down convert, rounding to odd (top) Arm’s documentation
svdiv_f32_mExperimental`sve`
  Divide Arm’s documentation
svdiv_f32_xExperimental`sve`
  Divide Arm’s documentation
svdiv_f32_zExperimental`sve`
  Divide Arm’s documentation
svdiv_f64_mExperimental`sve`
  Divide Arm’s documentation
svdiv_f64_xExperimental`sve`
  Divide Arm’s documentation
svdiv_f64_zExperimental`sve`
  Divide Arm’s documentation
svdiv_n_f32_mExperimental`sve`
  Divide Arm’s documentation
svdiv_n_f32_xExperimental`sve`
  Divide Arm’s documentation
svdiv_n_f32_zExperimental`sve`
  Divide Arm’s documentation
svdiv_n_f64_mExperimental`sve`
  Divide Arm’s documentation
svdiv_n_f64_xExperimental`sve`
  Divide Arm’s documentation
svdiv_n_f64_zExperimental`sve`
  Divide Arm’s documentation
svdiv_n_s32_mExperimental`sve`
  Divide Arm’s documentation
svdiv_n_s32_xExperimental`sve`
  Divide Arm’s documentation
svdiv_n_s32_zExperimental`sve`
  Divide Arm’s documentation
svdiv_n_s64_mExperimental`sve`
  Divide Arm’s documentation
svdiv_n_s64_xExperimental`sve`
  Divide Arm’s documentation
svdiv_n_s64_zExperimental`sve`
  Divide Arm’s documentation
svdiv_n_u32_mExperimental`sve`
  Divide Arm’s documentation
svdiv_n_u32_xExperimental`sve`
  Divide Arm’s documentation
svdiv_n_u32_zExperimental`sve`
  Divide Arm’s documentation
svdiv_n_u64_mExperimental`sve`
  Divide Arm’s documentation
svdiv_n_u64_xExperimental`sve`
  Divide Arm’s documentation
svdiv_n_u64_zExperimental`sve`
  Divide Arm’s documentation
svdiv_s32_mExperimental`sve`
  Divide Arm’s documentation
svdiv_s32_xExperimental`sve`
  Divide Arm’s documentation
svdiv_s32_zExperimental`sve`
  Divide Arm’s documentation
svdiv_s64_mExperimental`sve`
  Divide Arm’s documentation
svdiv_s64_xExperimental`sve`
  Divide Arm’s documentation
svdiv_s64_zExperimental`sve`
  Divide Arm’s documentation
svdiv_u32_mExperimental`sve`
  Divide Arm’s documentation
svdiv_u32_xExperimental`sve`
  Divide Arm’s documentation
svdiv_u32_zExperimental`sve`
  Divide Arm’s documentation
svdiv_u64_mExperimental`sve`
  Divide Arm’s documentation
svdiv_u64_xExperimental`sve`
  Divide Arm’s documentation
svdiv_u64_zExperimental`sve`
  Divide Arm’s documentation
svdivr_f32_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_f32_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_f32_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_f64_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_f64_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_f64_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_f32_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_f32_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_f32_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_f64_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_f64_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_f64_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_s32_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_s32_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_s32_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_s64_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_s64_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_s64_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_u32_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_u32_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_u32_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_u64_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_u64_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_n_u64_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_s32_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_s32_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_s32_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_s64_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_s64_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_s64_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_u32_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_u32_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_u32_zExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_u64_mExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_u64_xExperimental`sve`
  Divide reversed Arm’s documentation
svdivr_u64_zExperimental`sve`
  Divide reversed Arm’s documentation
svdot_lane_s32Experimental`sve`
  Dot product Arm’s documentation
svdot_lane_s64Experimental`sve`
  Dot product Arm’s documentation
svdot_lane_u32Experimental`sve`
  Dot product Arm’s documentation
svdot_lane_u64Experimental`sve`
  Dot product Arm’s documentation
svdot_n_s32Experimental`sve`
  Dot product Arm’s documentation
svdot_n_s64Experimental`sve`
  Dot product Arm’s documentation
svdot_n_u32Experimental`sve`
  Dot product Arm’s documentation
svdot_n_u64Experimental`sve`
  Dot product Arm’s documentation
svdot_s32Experimental`sve`
  Dot product Arm’s documentation
svdot_s64Experimental`sve`
  Dot product Arm’s documentation
svdot_u32Experimental`sve`
  Dot product Arm’s documentation
svdot_u64Experimental`sve`
  Dot product Arm’s documentation
svdup_lane_f32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_f64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_s8Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_s16Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_s32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_s64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_u8Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_u16Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_u32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_lane_u64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_b8Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_b16Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_b32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_b64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f32_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f32_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f32_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f64_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f64_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_f64_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s8Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s8_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s8_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s8_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s16Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s16_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s16_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s16_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s32_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s32_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s32_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s64_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s64_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_s64_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u8Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u8_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u8_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u8_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u16Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u32Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u64Experimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u16_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u16_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u16_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u32_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u32_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u32_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u64_mExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u64_xExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdup_n_u64_zExperimental`sve`
  Broadcast a scalar value Arm’s documentation
svdupq_lane_f32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_f64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_s8Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_s16Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_s32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_s64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_u8Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_u16Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_u32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_lane_u64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_b8Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_b16Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_b32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_b64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_f32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_f64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_s8Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_s16Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_s32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_s64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_u8Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_u16Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_u32Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
svdupq_n_u64Experimental`sve`
  Broadcast a quadword of scalars Arm’s documentation
sveor3_n_s8Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_s16Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_s32Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_s64Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_u8Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_u16Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_u32Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_n_u64Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_s8Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_s16Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_s32Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_s64Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_u8Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_u16Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_u32Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor3_u64Experimental`sve2` and `sve`
  Bitwise exclusive OR of three vectors Arm’s documentation
sveor_b_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s8_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s8_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s8_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s16_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s16_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s16_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s32_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s32_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s32_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s64_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s64_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_s64_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u8_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u8_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u8_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u16_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u16_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u16_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u32_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u32_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u32_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u64_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u64_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_n_u64_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s8_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s8_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s8_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s16_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s16_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s16_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s32_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s32_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s32_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s64_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s64_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_s64_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u8_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u8_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u8_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u16_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u16_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u16_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u32_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u32_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u32_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u64_mExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u64_xExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveor_u64_zExperimental`sve`
  Bitwise exclusive OR Arm’s documentation
sveorbt_n_s8Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_s16Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_s32Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_s64Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_u8Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_u16Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_u32Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_n_u64Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_s8Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_s16Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_s32Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_s64Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_u8Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_u16Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_u32Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveorbt_u64Experimental`sve2` and `sve`
  Interleaving exclusive OR (bottom, top) Arm’s documentation
sveortb_n_s8Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_s16Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_s32Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_s64Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_u8Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_u16Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_u32Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_n_u64Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_s8Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_s16Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_s32Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_s64Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_u8Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_u16Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_u32Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveortb_u64Experimental`sve2` and `sve`
  Interleaving exclusive OR (top, bottom) Arm’s documentation
sveorv_s8Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_s16Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_s32Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_s64Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_u8Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_u16Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_u32Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
sveorv_u64Experimental`sve`
  Bitwise exclusive OR reduction to scalar Arm’s documentation
svexpa_f32Experimental`sve`
  Floating-point exponential accelerator Arm’s documentation
svexpa_f64Experimental`sve`
  Floating-point exponential accelerator Arm’s documentation
svext_f32Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_f64Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_s8Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_s16Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_s32Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_s64Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_u8Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_u16Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_u32Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svext_u64Experimental`sve`
  Extract vector from pair of vectors Arm’s documentation
svextb_s16_mExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s16_xExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s16_zExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s32_mExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s32_xExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s32_zExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s64_mExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s64_xExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_s64_zExperimental`sve`
  Sign-extend the low 8 bits Arm’s documentation
svextb_u16_mExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u16_xExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u16_zExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u32_mExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u32_xExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u32_zExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u64_mExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u64_xExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svextb_u64_zExperimental`sve`
  Zero-extend the low 8 bits Arm’s documentation
svexth_s32_mExperimental`sve`
  Sign-extend the low 16 bits Arm’s documentation
svexth_s32_xExperimental`sve`
  Sign-extend the low 16 bits Arm’s documentation
svexth_s32_zExperimental`sve`
  Sign-extend the low 16 bits Arm’s documentation
svexth_s64_mExperimental`sve`
  Sign-extend the low 16 bits Arm’s documentation
svexth_s64_xExperimental`sve`
  Sign-extend the low 16 bits Arm’s documentation
svexth_s64_zExperimental`sve`
  Sign-extend the low 16 bits Arm’s documentation
svexth_u32_mExperimental`sve`
  Zero-extend the low 16 bits Arm’s documentation
svexth_u32_xExperimental`sve`
  Zero-extend the low 16 bits Arm’s documentation
svexth_u32_zExperimental`sve`
  Zero-extend the low 16 bits Arm’s documentation
svexth_u64_mExperimental`sve`
  Zero-extend the low 16 bits Arm’s documentation
svexth_u64_xExperimental`sve`
  Zero-extend the low 16 bits Arm’s documentation
svexth_u64_zExperimental`sve`
  Zero-extend the low 16 bits Arm’s documentation
svextw_s64_mExperimental`sve`
  Sign-extend the low 32 bits Arm’s documentation
svextw_s64_xExperimental`sve`
  Sign-extend the low 32 bits Arm’s documentation
svextw_s64_zExperimental`sve`
  Sign-extend the low 32 bits Arm’s documentation
svextw_u64_mExperimental`sve`
  Zero-extend the low 32 bits Arm’s documentation
svextw_u64_xExperimental`sve`
  Zero-extend the low 32 bits Arm’s documentation
svextw_u64_zExperimental`sve`
  Zero-extend the low 32 bits Arm’s documentation
svget2_f32Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_f64Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_s8Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_s16Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_s32Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_s64Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_u8Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_u16Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_u32Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget2_u64Experimental`sve`
  Extract one vector from a tuple of two vectors Arm’s documentation
svget3_f32Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_f64Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_s8Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_s16Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_s32Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_s64Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_u8Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_u16Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_u32Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget3_u64Experimental`sve`
  Extract one vector from a tuple of three vectors Arm’s documentation
svget4_f32Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_f64Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_s8Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_s16Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_s32Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_s64Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_u8Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_u16Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_u32Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svget4_u64Experimental`sve`
  Extract one vector from a tuple of four vectors Arm’s documentation
svhadd_n_s8_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s8_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s8_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s16_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s16_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s16_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s32_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s32_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s32_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s64_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s64_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_s64_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u8_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u8_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u8_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u16_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u16_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u16_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u32_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u32_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u32_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u64_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u64_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_n_u64_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s8_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s8_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s8_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s16_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s16_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s16_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s32_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s32_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s32_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s64_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s64_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_s64_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u8_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u8_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u8_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u16_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u16_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u16_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u32_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u32_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u32_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u64_mExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u64_xExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhadd_u64_zExperimental`sve2` and `sve`
  Halving add Arm’s documentation
svhistcnt_s32_zExperimental`sve2` and `sve`
  Count matching elements Arm’s documentation
svhistcnt_s64_zExperimental`sve2` and `sve`
  Count matching elements Arm’s documentation
svhistcnt_u32_zExperimental`sve2` and `sve`
  Count matching elements Arm’s documentation
svhistcnt_u64_zExperimental`sve2` and `sve`
  Count matching elements Arm’s documentation
svhistseg_s8Experimental`sve2` and `sve`
  Count matching elements in 128-bit segments Arm’s documentation
svhistseg_u8Experimental`sve2` and `sve`
  Count matching elements in 128-bit segments Arm’s documentation
svhsub_n_s8_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s8_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s8_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s16_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s16_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s16_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s32_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s32_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s32_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s64_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s64_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_s64_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u8_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u8_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u8_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u16_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u16_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u16_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u32_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u32_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u32_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u64_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u64_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_n_u64_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s8_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s8_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s8_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s16_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s16_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s16_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s32_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s32_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s32_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s64_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s64_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_s64_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u8_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u8_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u8_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u16_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u16_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u16_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u32_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u32_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u32_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u64_mExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u64_xExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsub_u64_zExperimental`sve2` and `sve`
  Halving subtract Arm’s documentation
svhsubr_n_s8_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s8_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s8_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s16_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s16_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s16_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s32_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s32_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s32_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s64_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s64_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_s64_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u8_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u8_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u8_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u16_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u16_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u16_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u32_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u32_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u32_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u64_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u64_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_n_u64_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s8_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s8_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s8_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s16_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s16_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s16_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s32_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s32_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s32_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s64_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s64_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_s64_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u8_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u8_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u8_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u16_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u16_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u16_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u32_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u32_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u32_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u64_mExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u64_xExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svhsubr_u64_zExperimental`sve2` and `sve`
  Halving subtract reversed Arm’s documentation
svindex_s8Experimental`sve`
  Create linear series Arm’s documentation
svindex_s16Experimental`sve`
  Create linear series Arm’s documentation
svindex_s32Experimental`sve`
  Create linear series Arm’s documentation
svindex_s64Experimental`sve`
  Create linear series Arm’s documentation
svindex_u8Experimental`sve`
  Create linear series Arm’s documentation
svindex_u16Experimental`sve`
  Create linear series Arm’s documentation
svindex_u32Experimental`sve`
  Create linear series Arm’s documentation
svindex_u64Experimental`sve`
  Create linear series Arm’s documentation
svinsr_n_f32Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_f64Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_s8Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_s16Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_s32Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_s64Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_u8Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_u16Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_u32Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svinsr_n_u64Experimental`sve`
  Insert scalar in shifted vector Arm’s documentation
svlasta_f32Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_f64Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_s8Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_s16Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_s32Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_s64Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_u8Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_u16Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_u32Experimental`sve`
  Extract element after last Arm’s documentation
svlasta_u64Experimental`sve`
  Extract element after last Arm’s documentation
svlastb_f32Experimental`sve`
  Extract last element Arm’s documentation
svlastb_f64Experimental`sve`
  Extract last element Arm’s documentation
svlastb_s8Experimental`sve`
  Extract last element Arm’s documentation
svlastb_s16Experimental`sve`
  Extract last element Arm’s documentation
svlastb_s32Experimental`sve`
  Extract last element Arm’s documentation
svlastb_s64Experimental`sve`
  Extract last element Arm’s documentation
svlastb_u8Experimental`sve`
  Extract last element Arm’s documentation
svlastb_u16Experimental`sve`
  Extract last element Arm’s documentation
svlastb_u32Experimental`sve`
  Extract last element Arm’s documentation
svlastb_u64Experimental`sve`
  Extract last element Arm’s documentation
svld1_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s32index_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s32index_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s32index_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s32offset_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s32offset_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s32offset_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s64index_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s64index_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s64index_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s64offset_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s64offset_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_s64offset_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_index_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_index_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_index_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_offset_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_offset_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_offset_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32base_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32index_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32index_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32index_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32offset_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32offset_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u32offset_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_index_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_index_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_index_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_offset_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_offset_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_offset_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64base_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64index_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64index_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64index_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64offset_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64offset_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_gather_u64offset_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_s8⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_s16⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_u8⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_u16⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_f32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_f64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_s8⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_s16⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_s32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_s64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_u8⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_u16⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_u32⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1_vnum_u64⚠Experimental`sve`
  Unextended load Arm’s documentation
svld1ro_f32⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_f64⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_s8⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_s16⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_s32⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_s64⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_u8⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_u16⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_u32⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1ro_u64⚠Experimental`f64mm` and `sve`
  Load and replicate 256 bits of data Arm’s documentation
svld1rq_f32⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_f64⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_s8⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_s16⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_s32⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_s64⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_u8⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_u16⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_u32⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1rq_u64⚠Experimental`sve`
  Load and replicate 128 bits of data Arm’s documentation
svld1sb_gather_s32offset_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_s32offset_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_s64offset_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_s64offset_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u32base_offset_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u32base_offset_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u32base_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u32base_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u32offset_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u32offset_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u64base_offset_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u64base_offset_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u64base_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u64base_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u64offset_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_gather_u64offset_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_s16⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_u16⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_vnum_s16⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_vnum_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_vnum_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_vnum_u16⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_vnum_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sb_vnum_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend Arm’s documentation
svld1sh_gather_s32index_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s32index_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s32offset_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s32offset_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s64index_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s64index_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s64offset_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_s64offset_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32base_index_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32base_index_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32base_offset_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32base_offset_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32base_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32base_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32index_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32index_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32offset_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u32offset_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64base_index_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64base_index_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64base_offset_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64base_offset_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64base_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64base_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64index_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64index_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64offset_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_gather_u64offset_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_vnum_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_vnum_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_vnum_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sh_vnum_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend Arm’s documentation
svld1sw_gather_s64index_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_s64index_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_s64offset_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_s64offset_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64base_index_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64base_index_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64base_offset_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64base_offset_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64base_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64base_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64index_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64index_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64offset_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_gather_u64offset_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_vnum_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1sw_vnum_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend Arm’s documentation
svld1ub_gather_s32offset_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_s32offset_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_s64offset_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_s64offset_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u32base_offset_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u32base_offset_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u32base_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u32base_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u32offset_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u32offset_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u64base_offset_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u64base_offset_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u64base_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u64base_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u64offset_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_gather_u64offset_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_s16⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_u16⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_vnum_s16⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_vnum_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_vnum_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_vnum_u16⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_vnum_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1ub_vnum_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend Arm’s documentation
svld1uh_gather_s32index_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s32index_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s32offset_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s32offset_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s64index_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s64index_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s64offset_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_s64offset_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32base_index_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32base_index_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32base_offset_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32base_offset_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32base_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32base_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32index_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32index_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32offset_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u32offset_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64base_index_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64base_index_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64base_offset_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64base_offset_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64base_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64base_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64index_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64index_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64offset_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_gather_u64offset_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_vnum_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_vnum_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_vnum_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uh_vnum_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend Arm’s documentation
svld1uw_gather_s64index_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_s64index_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_s64offset_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_s64offset_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64base_index_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64base_index_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64base_offset_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64base_offset_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64base_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64base_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64index_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64index_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64offset_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_gather_u64offset_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_vnum_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld1uw_vnum_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend Arm’s documentation
svld2_f32⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_f64⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_s8⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_s16⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_s32⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_s64⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_u8⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_u16⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_u32⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_u64⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_f32⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_f64⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_s8⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_s16⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_s32⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_s64⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_u8⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_u16⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_u32⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld2_vnum_u64⚠Experimental`sve`
  Load two-element tuples into two vectors Arm’s documentation
svld3_f32⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_f64⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_s8⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_s16⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_s32⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_s64⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_u8⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_u16⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_u32⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_u64⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_f32⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_f64⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_s8⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_s16⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_s32⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_s64⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_u8⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_u16⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_u32⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld3_vnum_u64⚠Experimental`sve`
  Load three-element tuples into three vectors Arm’s documentation
svld4_f32⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_f64⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_s8⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_s16⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_s32⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_s64⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_u8⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_u16⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_u32⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_u64⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_f32⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_f64⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_s8⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_s16⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_s32⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_s64⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_u8⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_u16⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_u32⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svld4_vnum_u64⚠Experimental`sve`
  Load four-element tuples into four vectors Arm’s documentation
svldff1_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s32index_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s32index_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s32index_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s32offset_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s32offset_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s32offset_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s64index_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s64index_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s64index_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s64offset_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s64offset_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_s64offset_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_index_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_index_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_index_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_offset_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_offset_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_offset_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32base_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32index_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32index_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32index_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32offset_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32offset_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u32offset_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_index_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_index_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_index_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_offset_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_offset_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_offset_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64base_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64index_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64index_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64index_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64offset_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64offset_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_gather_u64offset_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_s8⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_s16⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_u8⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_u16⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_f32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_f64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_s8⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_s16⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_s32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_s64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_u8⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_u16⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_u32⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1_vnum_u64⚠Experimental`sve`
  Unextended load, first-faulting Arm’s documentation
svldff1sb_gather_s32offset_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_s32offset_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_s64offset_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_s64offset_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u32base_offset_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u32base_offset_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u32base_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u32base_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u32offset_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u32offset_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u64base_offset_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u64base_offset_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u64base_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u64base_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u64offset_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_gather_u64offset_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_s16⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_u16⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_vnum_s16⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_vnum_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_vnum_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_vnum_u16⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_vnum_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sb_vnum_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s32index_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s32index_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s32offset_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s32offset_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s64index_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s64index_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s64offset_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_s64offset_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32base_index_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32base_index_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32base_offset_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32base_offset_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32base_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32base_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32index_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32index_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32offset_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u32offset_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64base_index_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64base_index_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64base_offset_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64base_offset_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64base_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64base_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64index_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64index_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64offset_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_gather_u64offset_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_vnum_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_vnum_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_vnum_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sh_vnum_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_s64index_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_s64index_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_s64offset_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_s64offset_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64base_index_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64base_index_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64base_offset_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64base_offset_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64base_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64base_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64index_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64index_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64offset_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_gather_u64offset_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_vnum_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1sw_vnum_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, first-faulting Arm’s documentation
svldff1ub_gather_s32offset_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_s32offset_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_s64offset_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_s64offset_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u32base_offset_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u32base_offset_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u32base_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u32base_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u32offset_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u32offset_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u64base_offset_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u64base_offset_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u64base_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u64base_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u64offset_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_gather_u64offset_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_s16⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_u16⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_vnum_s16⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_vnum_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_vnum_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_vnum_u16⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_vnum_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1ub_vnum_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s32index_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s32index_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s32offset_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s32offset_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s64index_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s64index_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s64offset_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_s64offset_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32base_index_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32base_index_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32base_offset_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32base_offset_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32base_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32base_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32index_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32index_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32offset_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u32offset_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64base_index_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64base_index_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64base_offset_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64base_offset_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64base_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64base_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64index_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64index_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64offset_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_gather_u64offset_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_vnum_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_vnum_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_vnum_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uh_vnum_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_s64index_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_s64index_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_s64offset_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_s64offset_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64base_index_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64base_index_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64base_offset_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64base_offset_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64base_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64base_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64index_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64index_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64offset_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_gather_u64offset_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_vnum_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldff1uw_vnum_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, first-faulting Arm’s documentation
svldnf1_f32⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_f64⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_s8⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_s16⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_s32⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_s64⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_u8⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_u16⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_u32⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_u64⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_f32⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_f64⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_s8⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_s16⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_s32⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_s64⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_u8⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_u16⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_u32⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1_vnum_u64⚠Experimental`sve`
  Unextended load, non-faulting Arm’s documentation
svldnf1sb_s16⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_u16⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_vnum_s16⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_vnum_s32⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_vnum_s64⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_vnum_u16⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_vnum_u32⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sb_vnum_u64⚠Experimental`sve`
  Load 8-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_vnum_s32⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_vnum_s64⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_vnum_u32⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sh_vnum_u64⚠Experimental`sve`
  Load 16-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sw_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sw_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sw_vnum_s64⚠Experimental`sve`
  Load 32-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1sw_vnum_u64⚠Experimental`sve`
  Load 32-bit data and sign-extend, non-faulting Arm’s documentation
svldnf1ub_s16⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_u16⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_vnum_s16⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_vnum_s32⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_vnum_s64⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_vnum_u16⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_vnum_u32⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1ub_vnum_u64⚠Experimental`sve`
  Load 8-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_vnum_s32⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_vnum_s64⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_vnum_u32⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uh_vnum_u64⚠Experimental`sve`
  Load 16-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uw_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uw_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uw_vnum_s64⚠Experimental`sve`
  Load 32-bit data and zero-extend, non-faulting Arm’s documentation
svldnf1uw_vnum_u64⚠Experimental`sve`
  Load 32-bit data and zero-extend, non-faulting Arm’s documentation
svldnt1_f32⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_f64⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_s64index_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_s64index_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_s64index_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_s64offset_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_f32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_index_f32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_index_s32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_index_u32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_offset_f32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_s32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32base_u32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32offset_f32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32offset_s32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u32offset_u32⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_index_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_index_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_index_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_offset_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64index_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64index_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64index_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64offset_f64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_s8⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_s16⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_s32⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_s64⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_u8⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_u16⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_u32⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_u64⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_f32⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_f64⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_s8⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_s16⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_s32⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_s64⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_u8⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_u16⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_u32⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1_vnum_u64⚠Experimental`sve`
  Unextended load, non-temporal Arm’s documentation
svldnt1sb_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u32base_s32⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u32base_u32⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u32offset_s32⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u32offset_u32⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sb_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_s64index_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_s64index_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32base_index_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32base_index_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32base_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32base_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32offset_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u32offset_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64base_index_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64base_index_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64index_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64index_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sh_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_s64index_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_s64index_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64base_index_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64base_index_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64index_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64index_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1sw_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and sign-extend, non-temporal Arm’s documentation
svldnt1ub_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u32base_s32⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u32base_u32⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u32offset_s32⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u32offset_u32⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1ub_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Load 8-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_s64index_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_s64index_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32base_index_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32base_index_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32base_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32base_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32offset_s32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u32offset_u32⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64base_index_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64base_index_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64index_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64index_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uh_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Load 16-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_s64index_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_s64index_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_s64offset_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_s64offset_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64base_index_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64base_index_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64base_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64base_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64index_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64index_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64offset_s64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svldnt1uw_gather_u64offset_u64⚠Experimental`sve2` and `sve`
  Load 32-bit data and zero-extend, non-temporal Arm’s documentation
svlen_f32Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_f64Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_s8Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_s16Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_s32Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_s64Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_u8Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_u16Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_u32Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlen_u64Experimental`sve`
  Count the number of elements in a full vector Arm’s documentation
svlogb_f32_mExperimental`sve2` and `sve`
  Base 2 logarithm as integer Arm’s documentation
svlogb_f32_xExperimental`sve2` and `sve`
  Base 2 logarithm as integer Arm’s documentation
svlogb_f32_zExperimental`sve2` and `sve`
  Base 2 logarithm as integer Arm’s documentation
svlogb_f64_mExperimental`sve2` and `sve`
  Base 2 logarithm as integer Arm’s documentation
svlogb_f64_xExperimental`sve2` and `sve`
  Base 2 logarithm as integer Arm’s documentation
svlogb_f64_zExperimental`sve2` and `sve`
  Base 2 logarithm as integer Arm’s documentation
svlsl_n_s8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s64_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s64_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_s64_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u64_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u64_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_n_u64_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s64_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s64_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_s64_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u64_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u64_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_u64_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_s32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_n_u32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_s32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u8_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u8_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u8_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u16_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u16_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u16_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u32_mExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u32_xExperimental`sve`
  Logical shift left Arm’s documentation
svlsl_wide_u32_zExperimental`sve`
  Logical shift left Arm’s documentation
svlsr_n_u8_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u8_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u8_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u16_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u16_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u16_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u32_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u32_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u32_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u64_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u64_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_n_u64_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u8_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u8_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u8_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u16_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u16_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u16_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u32_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u32_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u32_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u64_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u64_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_u64_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u8_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u8_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u8_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u16_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u16_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u16_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u32_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u32_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_n_u32_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u8_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u8_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u8_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u16_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u16_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u16_zExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u32_mExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u32_xExperimental`sve`
  Logical shift right Arm’s documentation
svlsr_wide_u32_zExperimental`sve`
  Logical shift right Arm’s documentation
svmad_f32_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_f32_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_f32_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_f64_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_f64_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_f64_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_f32_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_f32_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_f32_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_f64_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_f64_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_f64_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s8_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s8_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s8_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s16_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s16_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s16_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s32_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s32_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s32_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s64_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s64_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_s64_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u8_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u8_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u8_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u16_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u16_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u16_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u32_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u32_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u32_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u64_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u64_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_n_u64_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s8_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s8_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s8_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s16_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s16_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s16_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s32_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s32_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s32_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s64_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s64_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_s64_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u8_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u8_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u8_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u16_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u16_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u16_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u32_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u32_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u32_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u64_mExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u64_xExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmad_u64_zExperimental`sve`
  Multiply-add, multiplicand first Arm’s documentation
svmatch_s8Experimental`sve2` and `sve`
  Detect any matching elements Arm’s documentation
svmatch_s16Experimental`sve2` and `sve`
  Detect any matching elements Arm’s documentation
svmatch_u8Experimental`sve2` and `sve`
  Detect any matching elements Arm’s documentation
svmatch_u16Experimental`sve2` and `sve`
  Detect any matching elements Arm’s documentation
svmax_f32_mExperimental`sve`
  Maximum Arm’s documentation
svmax_f32_xExperimental`sve`
  Maximum Arm’s documentation
svmax_f32_zExperimental`sve`
  Maximum Arm’s documentation
svmax_f64_mExperimental`sve`
  Maximum Arm’s documentation
svmax_f64_xExperimental`sve`
  Maximum Arm’s documentation
svmax_f64_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_f32_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_f32_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_f32_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_f64_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_f64_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_f64_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s8_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s8_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s8_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s16_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s16_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s16_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s32_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s32_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s32_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s64_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s64_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_s64_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u8_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u8_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u8_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u16_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u16_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u16_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u32_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u32_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u32_zExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u64_mExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u64_xExperimental`sve`
  Maximum Arm’s documentation
svmax_n_u64_zExperimental`sve`
  Maximum Arm’s documentation
svmax_s8_mExperimental`sve`
  Maximum Arm’s documentation
svmax_s8_xExperimental`sve`
  Maximum Arm’s documentation
svmax_s8_zExperimental`sve`
  Maximum Arm’s documentation
svmax_s16_mExperimental`sve`
  Maximum Arm’s documentation
svmax_s16_xExperimental`sve`
  Maximum Arm’s documentation
svmax_s16_zExperimental`sve`
  Maximum Arm’s documentation
svmax_s32_mExperimental`sve`
  Maximum Arm’s documentation
svmax_s32_xExperimental`sve`
  Maximum Arm’s documentation
svmax_s32_zExperimental`sve`
  Maximum Arm’s documentation
svmax_s64_mExperimental`sve`
  Maximum Arm’s documentation
svmax_s64_xExperimental`sve`
  Maximum Arm’s documentation
svmax_s64_zExperimental`sve`
  Maximum Arm’s documentation
svmax_u8_mExperimental`sve`
  Maximum Arm’s documentation
svmax_u8_xExperimental`sve`
  Maximum Arm’s documentation
svmax_u8_zExperimental`sve`
  Maximum Arm’s documentation
svmax_u16_mExperimental`sve`
  Maximum Arm’s documentation
svmax_u16_xExperimental`sve`
  Maximum Arm’s documentation
svmax_u16_zExperimental`sve`
  Maximum Arm’s documentation
svmax_u32_mExperimental`sve`
  Maximum Arm’s documentation
svmax_u32_xExperimental`sve`
  Maximum Arm’s documentation
svmax_u32_zExperimental`sve`
  Maximum Arm’s documentation
svmax_u64_mExperimental`sve`
  Maximum Arm’s documentation
svmax_u64_xExperimental`sve`
  Maximum Arm’s documentation
svmax_u64_zExperimental`sve`
  Maximum Arm’s documentation
svmaxnm_f32_mExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_f32_xExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_f32_zExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_f64_mExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_f64_xExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_f64_zExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_n_f32_mExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_n_f32_xExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_n_f32_zExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_n_f64_mExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_n_f64_xExperimental`sve`
  Maximum number Arm’s documentation
svmaxnm_n_f64_zExperimental`sve`
  Maximum number Arm’s documentation
svmaxnmp_f32_mExperimental`sve2` and `sve`
  Maximum number pairwise Arm’s documentation
svmaxnmp_f32_xExperimental`sve2` and `sve`
  Maximum number pairwise Arm’s documentation
svmaxnmp_f64_mExperimental`sve2` and `sve`
  Maximum number pairwise Arm’s documentation
svmaxnmp_f64_xExperimental`sve2` and `sve`
  Maximum number pairwise Arm’s documentation
svmaxnmv_f32Experimental`sve`
  Maximum number reduction to scalar Arm’s documentation
svmaxnmv_f64Experimental`sve`
  Maximum number reduction to scalar Arm’s documentation
svmaxp_f32_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_f32_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_f64_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_f64_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s8_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s8_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s16_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s16_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s32_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s32_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s64_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_s64_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u8_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u8_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u16_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u16_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u32_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u32_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u64_mExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxp_u64_xExperimental`sve2` and `sve`
  Maximum pairwise Arm’s documentation
svmaxv_f32Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_f64Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_s8Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_s16Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_s32Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_s64Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_u8Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_u16Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_u32Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmaxv_u64Experimental`sve`
  Maximum reduction to scalar Arm’s documentation
svmin_f32_mExperimental`sve`
  Minimum Arm’s documentation
svmin_f32_xExperimental`sve`
  Minimum Arm’s documentation
svmin_f32_zExperimental`sve`
  Minimum Arm’s documentation
svmin_f64_mExperimental`sve`
  Minimum Arm’s documentation
svmin_f64_xExperimental`sve`
  Minimum Arm’s documentation
svmin_f64_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_f32_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_f32_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_f32_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_f64_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_f64_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_f64_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s8_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s8_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s8_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s16_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s16_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s16_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s32_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s32_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s32_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s64_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s64_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_s64_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u8_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u8_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u8_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u16_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u16_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u16_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u32_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u32_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u32_zExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u64_mExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u64_xExperimental`sve`
  Minimum Arm’s documentation
svmin_n_u64_zExperimental`sve`
  Minimum Arm’s documentation
svmin_s8_mExperimental`sve`
  Minimum Arm’s documentation
svmin_s8_xExperimental`sve`
  Minimum Arm’s documentation
svmin_s8_zExperimental`sve`
  Minimum Arm’s documentation
svmin_s16_mExperimental`sve`
  Minimum Arm’s documentation
svmin_s16_xExperimental`sve`
  Minimum Arm’s documentation
svmin_s16_zExperimental`sve`
  Minimum Arm’s documentation
svmin_s32_mExperimental`sve`
  Minimum Arm’s documentation
svmin_s32_xExperimental`sve`
  Minimum Arm’s documentation
svmin_s32_zExperimental`sve`
  Minimum Arm’s documentation
svmin_s64_mExperimental`sve`
  Minimum Arm’s documentation
svmin_s64_xExperimental`sve`
  Minimum Arm’s documentation
svmin_s64_zExperimental`sve`
  Minimum Arm’s documentation
svmin_u8_mExperimental`sve`
  Minimum Arm’s documentation
svmin_u8_xExperimental`sve`
  Minimum Arm’s documentation
svmin_u8_zExperimental`sve`
  Minimum Arm’s documentation
svmin_u16_mExperimental`sve`
  Minimum Arm’s documentation
svmin_u16_xExperimental`sve`
  Minimum Arm’s documentation
svmin_u16_zExperimental`sve`
  Minimum Arm’s documentation
svmin_u32_mExperimental`sve`
  Minimum Arm’s documentation
svmin_u32_xExperimental`sve`
  Minimum Arm’s documentation
svmin_u32_zExperimental`sve`
  Minimum Arm’s documentation
svmin_u64_mExperimental`sve`
  Minimum Arm’s documentation
svmin_u64_xExperimental`sve`
  Minimum Arm’s documentation
svmin_u64_zExperimental`sve`
  Minimum Arm’s documentation
svminnm_f32_mExperimental`sve`
  Minimum number Arm’s documentation
svminnm_f32_xExperimental`sve`
  Minimum number Arm’s documentation
svminnm_f32_zExperimental`sve`
  Minimum number Arm’s documentation
svminnm_f64_mExperimental`sve`
  Minimum number Arm’s documentation
svminnm_f64_xExperimental`sve`
  Minimum number Arm’s documentation
svminnm_f64_zExperimental`sve`
  Minimum number Arm’s documentation
svminnm_n_f32_mExperimental`sve`
  Minimum number Arm’s documentation
svminnm_n_f32_xExperimental`sve`
  Minimum number Arm’s documentation
svminnm_n_f32_zExperimental`sve`
  Minimum number Arm’s documentation
svminnm_n_f64_mExperimental`sve`
  Minimum number Arm’s documentation
svminnm_n_f64_xExperimental`sve`
  Minimum number Arm’s documentation
svminnm_n_f64_zExperimental`sve`
  Minimum number Arm’s documentation
svminnmp_f32_mExperimental`sve2` and `sve`
  Minimum number pairwise Arm’s documentation
svminnmp_f32_xExperimental`sve2` and `sve`
  Minimum number pairwise Arm’s documentation
svminnmp_f64_mExperimental`sve2` and `sve`
  Minimum number pairwise Arm’s documentation
svminnmp_f64_xExperimental`sve2` and `sve`
  Minimum number pairwise Arm’s documentation
svminnmv_f32Experimental`sve`
  Minimum number reduction to scalar Arm’s documentation
svminnmv_f64Experimental`sve`
  Minimum number reduction to scalar Arm’s documentation
svminp_f32_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_f32_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_f64_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_f64_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s8_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s8_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s16_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s16_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s32_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s32_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s64_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_s64_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u8_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u8_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u16_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u16_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u32_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u32_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u64_mExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminp_u64_xExperimental`sve2` and `sve`
  Minimum pairwise Arm’s documentation
svminv_f32Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_f64Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_s8Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_s16Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_s32Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_s64Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_u8Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_u16Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_u32Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svminv_u64Experimental`sve`
  Minimum reduction to scalar Arm’s documentation
svmla_f32_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_f32_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_f32_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_f64_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_f64_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_f64_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_f32Experimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_f64Experimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_s16Experimental`sve2` and `sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_s32Experimental`sve2` and `sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_s64Experimental`sve2` and `sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_u16Experimental`sve2` and `sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_u32Experimental`sve2` and `sve`
  Multiply-add, addend first Arm’s documentation
svmla_lane_u64Experimental`sve2` and `sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_f32_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_f32_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_f32_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_f64_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_f64_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_f64_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s8_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s8_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s8_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s16_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s16_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s16_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s32_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s32_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s32_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s64_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s64_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_s64_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u8_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u8_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u8_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u16_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u16_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u16_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u32_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u32_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u32_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u64_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u64_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_n_u64_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s8_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s8_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s8_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s16_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s16_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s16_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s32_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s32_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s32_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s64_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s64_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_s64_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u8_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u8_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u8_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u16_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u16_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u16_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u32_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u32_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u32_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u64_mExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u64_xExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmla_u64_zExperimental`sve`
  Multiply-add, addend first Arm’s documentation
svmlalb_lane_s32Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_lane_s64Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_lane_u32Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_lane_u64Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_n_s16Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_n_s32Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_n_s64Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_n_u16Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_n_u32Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_n_u64Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_s16Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_s32Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_s64Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_u16Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_u32Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalb_u64Experimental`sve2` and `sve`
  Multiply-add long (bottom) Arm’s documentation
svmlalt_lane_s32Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_lane_s64Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_lane_u32Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_lane_u64Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_n_s16Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_n_s32Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_n_s64Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_n_u16Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_n_u32Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_n_u64Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_s16Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_s32Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_s64Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_u16Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_u32Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmlalt_u64Experimental`sve2` and `sve`
  Multiply-add long (top) Arm’s documentation
svmls_f32_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_f32_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_f32_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_f64_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_f64_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_f64_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_f32Experimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_f64Experimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_s16Experimental`sve2` and `sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_s32Experimental`sve2` and `sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_s64Experimental`sve2` and `sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_u16Experimental`sve2` and `sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_u32Experimental`sve2` and `sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_lane_u64Experimental`sve2` and `sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_f32_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_f32_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_f32_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_f64_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_f64_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_f64_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s8_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s8_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s8_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s16_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s16_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s16_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s32_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s32_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s32_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s64_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s64_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_s64_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u8_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u8_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u8_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u16_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u16_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u16_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u32_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u32_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u32_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u64_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u64_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_n_u64_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s8_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s8_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s8_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s16_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s16_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s16_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s32_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s32_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s32_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s64_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s64_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_s64_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u8_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u8_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u8_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u16_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u16_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u16_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u32_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u32_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u32_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u64_mExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u64_xExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmls_u64_zExperimental`sve`
  Multiply-subtract, minuend first Arm’s documentation
svmlslb_lane_s32Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_lane_s64Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_lane_u32Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_lane_u64Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_n_s16Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_n_s32Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_n_s64Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_n_u16Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_n_u32Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_n_u64Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_s16Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_s32Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_s64Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_u16Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_u32Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslb_u64Experimental`sve2` and `sve`
  Multiply-subtract long (bottom) Arm’s documentation
svmlslt_lane_s32Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_lane_s64Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_lane_u32Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_lane_u64Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_n_s16Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_n_s32Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_n_s64Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_n_u16Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_n_u32Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_n_u64Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_s16Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_s32Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_s64Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_u16Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_u32Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmlslt_u64Experimental`sve2` and `sve`
  Multiply-subtract long (top) Arm’s documentation
svmmla_f32Experimental`f32mm` and `sve`
  Matrix multiply-accumulate Arm’s documentation
svmmla_f64Experimental`f64mm` and `sve`
  Matrix multiply-accumulate Arm’s documentation
svmmla_s32Experimental`i8mm` and `sve`
  Matrix multiply-accumulate Arm’s documentation
svmmla_u32Experimental`i8mm` and `sve`
  Matrix multiply-accumulate Arm’s documentation
svmov_b_zExperimental`sve`
  Move Arm’s documentation
svmovlb_s16Experimental`sve2` and `sve`
  Move long (bottom) Arm’s documentation
svmovlb_s32Experimental`sve2` and `sve`
  Move long (bottom) Arm’s documentation
svmovlb_s64Experimental`sve2` and `sve`
  Move long (bottom) Arm’s documentation
svmovlb_u16Experimental`sve2` and `sve`
  Move long (bottom) Arm’s documentation
svmovlb_u32Experimental`sve2` and `sve`
  Move long (bottom) Arm’s documentation
svmovlb_u64Experimental`sve2` and `sve`
  Move long (bottom) Arm’s documentation
svmovlt_s16Experimental`sve2` and `sve`
  Move long (top) Arm’s documentation
svmovlt_s32Experimental`sve2` and `sve`
  Move long (top) Arm’s documentation
svmovlt_s64Experimental`sve2` and `sve`
  Move long (top) Arm’s documentation
svmovlt_u16Experimental`sve2` and `sve`
  Move long (top) Arm’s documentation
svmovlt_u32Experimental`sve2` and `sve`
  Move long (top) Arm’s documentation
svmovlt_u64Experimental`sve2` and `sve`
  Move long (top) Arm’s documentation
svmsb_f32_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_f32_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_f32_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_f64_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_f64_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_f64_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_f32_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_f32_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_f32_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_f64_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_f64_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_f64_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s8_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s8_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s8_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s16_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s16_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s16_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s32_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s32_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s32_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s64_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s64_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_s64_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u8_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u8_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u8_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u16_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u16_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u16_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u32_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u32_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u32_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u64_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u64_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_n_u64_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s8_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s8_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s8_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s16_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s16_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s16_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s32_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s32_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s32_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s64_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s64_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_s64_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u8_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u8_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u8_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u16_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u16_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u16_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u32_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u32_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u32_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u64_mExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u64_xExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmsb_u64_zExperimental`sve`
  Multiply-subtract, multiplicand first Arm’s documentation
svmul_f32_mExperimental`sve`
  Multiply Arm’s documentation
svmul_f32_xExperimental`sve`
  Multiply Arm’s documentation
svmul_f32_zExperimental`sve`
  Multiply Arm’s documentation
svmul_f64_mExperimental`sve`
  Multiply Arm’s documentation
svmul_f64_xExperimental`sve`
  Multiply Arm’s documentation
svmul_f64_zExperimental`sve`
  Multiply Arm’s documentation
svmul_lane_f32Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_f64Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_s16Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_s32Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_s64Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_u16Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_u32Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_lane_u64Experimental`sve2` and `sve`
  Multiply Arm’s documentation
svmul_n_f32_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_f32_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_f32_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_f64_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_f64_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_f64_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s8_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s8_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s8_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s16_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s16_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s16_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s32_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s32_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s32_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s64_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s64_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_s64_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u8_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u8_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u8_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u16_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u16_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u16_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u32_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u32_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u32_zExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u64_mExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u64_xExperimental`sve`
  Multiply Arm’s documentation
svmul_n_u64_zExperimental`sve`
  Multiply Arm’s documentation
svmul_s8_mExperimental`sve`
  Multiply Arm’s documentation
svmul_s8_xExperimental`sve`
  Multiply Arm’s documentation
svmul_s8_zExperimental`sve`
  Multiply Arm’s documentation
svmul_s16_mExperimental`sve`
  Multiply Arm’s documentation
svmul_s16_xExperimental`sve`
  Multiply Arm’s documentation
svmul_s16_zExperimental`sve`
  Multiply Arm’s documentation
svmul_s32_mExperimental`sve`
  Multiply Arm’s documentation
svmul_s32_xExperimental`sve`
  Multiply Arm’s documentation
svmul_s32_zExperimental`sve`
  Multiply Arm’s documentation
svmul_s64_mExperimental`sve`
  Multiply Arm’s documentation
svmul_s64_xExperimental`sve`
  Multiply Arm’s documentation
svmul_s64_zExperimental`sve`
  Multiply Arm’s documentation
svmul_u8_mExperimental`sve`
  Multiply Arm’s documentation
svmul_u8_xExperimental`sve`
  Multiply Arm’s documentation
svmul_u8_zExperimental`sve`
  Multiply Arm’s documentation
svmul_u16_mExperimental`sve`
  Multiply Arm’s documentation
svmul_u16_xExperimental`sve`
  Multiply Arm’s documentation
svmul_u16_zExperimental`sve`
  Multiply Arm’s documentation
svmul_u32_mExperimental`sve`
  Multiply Arm’s documentation
svmul_u32_xExperimental`sve`
  Multiply Arm’s documentation
svmul_u32_zExperimental`sve`
  Multiply Arm’s documentation
svmul_u64_mExperimental`sve`
  Multiply Arm’s documentation
svmul_u64_xExperimental`sve`
  Multiply Arm’s documentation
svmul_u64_zExperimental`sve`
  Multiply Arm’s documentation
svmulh_n_s8_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s8_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s8_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s16_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s16_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s16_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s32_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s32_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s32_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s64_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s64_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_s64_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u8_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u8_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u8_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u16_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u16_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u16_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u32_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u32_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u32_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u64_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u64_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_n_u64_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s8_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s8_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s8_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s16_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s16_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s16_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s32_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s32_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s32_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s64_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s64_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_s64_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u8_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u8_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u8_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u16_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u16_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u16_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u32_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u32_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u32_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u64_mExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u64_xExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmulh_u64_zExperimental`sve`
  Multiply, returning high-half Arm’s documentation
svmullb_lane_s32Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_lane_s64Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_lane_u32Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_lane_u64Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_n_s16Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_n_s32Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_n_s64Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_n_u16Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_n_u32Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_n_u64Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_s16Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_s32Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_s64Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_u16Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_u32Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullb_u64Experimental`sve2` and `sve`
  Multiply long (bottom) Arm’s documentation
svmullt_lane_s32Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_lane_s64Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_lane_u32Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_lane_u64Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_n_s16Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_n_s32Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_n_s64Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_n_u16Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_n_u32Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_n_u64Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_s16Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_s32Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_s64Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_u16Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_u32Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmullt_u64Experimental`sve2` and `sve`
  Multiply long (top) Arm’s documentation
svmulx_f32_mExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_f32_xExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_f32_zExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_f64_mExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_f64_xExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_f64_zExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_n_f32_mExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_n_f32_xExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_n_f32_zExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_n_f64_mExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_n_f64_xExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svmulx_n_f64_zExperimental`sve`
  Multiply extended (∞×0=2) Arm’s documentation
svnand_b_zExperimental`sve`
  Bitwise NAND Arm’s documentation
svnbsl_n_s8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_s16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_s32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_s64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_u8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_u16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_u32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_n_u64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_s8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_s16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_s32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_s64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_u8Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_u16Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_u32Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svnbsl_u64Experimental`sve2` and `sve`
  Bitwise select Arm’s documentation
svneg_f32_mExperimental`sve`
  Negate Arm’s documentation
svneg_f32_xExperimental`sve`
  Negate Arm’s documentation
svneg_f32_zExperimental`sve`
  Negate Arm’s documentation
svneg_f64_mExperimental`sve`
  Negate Arm’s documentation
svneg_f64_xExperimental`sve`
  Negate Arm’s documentation
svneg_f64_zExperimental`sve`
  Negate Arm’s documentation
svneg_s8_mExperimental`sve`
  Negate Arm’s documentation
svneg_s8_xExperimental`sve`
  Negate Arm’s documentation
svneg_s8_zExperimental`sve`
  Negate Arm’s documentation
svneg_s16_mExperimental`sve`
  Negate Arm’s documentation
svneg_s16_xExperimental`sve`
  Negate Arm’s documentation
svneg_s16_zExperimental`sve`
  Negate Arm’s documentation
svneg_s32_mExperimental`sve`
  Negate Arm’s documentation
svneg_s32_xExperimental`sve`
  Negate Arm’s documentation
svneg_s32_zExperimental`sve`
  Negate Arm’s documentation
svneg_s64_mExperimental`sve`
  Negate Arm’s documentation
svneg_s64_xExperimental`sve`
  Negate Arm’s documentation
svneg_s64_zExperimental`sve`
  Negate Arm’s documentation
svnmad_f32_mExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_f32_xExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_f32_zExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_f64_mExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_f64_xExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_f64_zExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_n_f32_mExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_n_f32_xExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_n_f32_zExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_n_f64_mExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_n_f64_xExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmad_n_f64_zExperimental`sve`
  Negated multiply-add, multiplicand first Arm’s documentation
svnmatch_s8Experimental`sve2` and `sve`
  Detect no matching elements Arm’s documentation
svnmatch_s16Experimental`sve2` and `sve`
  Detect no matching elements Arm’s documentation
svnmatch_u8Experimental`sve2` and `sve`
  Detect no matching elements Arm’s documentation
svnmatch_u16Experimental`sve2` and `sve`
  Detect no matching elements Arm’s documentation
svnmla_f32_mExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_f32_xExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_f32_zExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_f64_mExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_f64_xExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_f64_zExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_n_f32_mExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_n_f32_xExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_n_f32_zExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_n_f64_mExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_n_f64_xExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmla_n_f64_zExperimental`sve`
  Negated multiply-add, addend first Arm’s documentation
svnmls_f32_mExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_f32_xExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_f32_zExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_f64_mExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_f64_xExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_f64_zExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_n_f32_mExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_n_f32_xExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_n_f32_zExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_n_f64_mExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_n_f64_xExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmls_n_f64_zExperimental`sve`
  Negated multiply-subtract, minuend first Arm’s documentation
svnmsb_f32_mExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_f32_xExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_f32_zExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_f64_mExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_f64_xExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_f64_zExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_n_f32_mExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_n_f32_xExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_n_f32_zExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_n_f64_mExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_n_f64_xExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnmsb_n_f64_zExperimental`sve`
  Negated multiply-subtract, multiplicand first Arm’s documentation
svnor_b_zExperimental`sve`
  Bitwise NOR Arm’s documentation
svnot_b_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s8_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s8_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s8_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s16_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s16_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s16_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s32_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s32_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s32_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s64_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s64_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_s64_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u8_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u8_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u8_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u16_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u16_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u16_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u32_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u32_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u32_zExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u64_mExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u64_xExperimental`sve`
  Bitwise invert Arm’s documentation
svnot_u64_zExperimental`sve`
  Bitwise invert Arm’s documentation
svorn_b_zExperimental`sve`
  Bitwise inclusive OR, inverting second argument Arm’s documentation
svorr_b_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s8_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s8_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s8_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s16_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s16_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s16_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s32_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s32_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s32_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s64_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s64_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_s64_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u8_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u8_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u8_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u16_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u16_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u16_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u32_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u32_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u32_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u64_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u64_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_n_u64_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s8_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s8_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s8_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s16_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s16_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s16_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s32_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s32_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s32_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s64_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s64_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_s64_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u8_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u8_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u8_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u16_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u16_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u16_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u32_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u32_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u32_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u64_mExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u64_xExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorr_u64_zExperimental`sve`
  Bitwise inclusive OR Arm’s documentation
svorv_s8Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_s16Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_s32Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_s64Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_u8Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_u16Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_u32Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svorv_u64Experimental`sve`
  Bitwise inclusive OR reduction to scalar Arm’s documentation
svpfalse_bExperimental`sve`
  Set all predicate elements to false Arm’s documentation
svpfirst_bExperimental`sve`
  Set the first active predicate element to true Arm’s documentation
svpmul_n_u8Experimental`sve2` and `sve`
  Polynomial multiply Arm’s documentation
svpmul_u8Experimental`sve2` and `sve`
  Polynomial multiply Arm’s documentation
svpmullb_n_u16Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_n_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_pair_n_u8Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_pair_n_u32Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_pair_n_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_pair_u8Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_pair_u32Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_pair_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_u16Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullb_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (bottom) Arm’s documentation
svpmullt_n_u16Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_n_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_pair_n_u8Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_pair_n_u32Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_pair_n_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_pair_u8Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_pair_u32Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_pair_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_u16Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpmullt_u64Experimental`sve2-aes` and `sve2` and `sve`
  Polynomial multiply long (top) Arm’s documentation
svpnext_b8Experimental`sve`
  Find next active predicate Arm’s documentation
svpnext_b16Experimental`sve`
  Find next active predicate Arm’s documentation
svpnext_b32Experimental`sve`
  Find next active predicate Arm’s documentation
svpnext_b64Experimental`sve`
  Find next active predicate Arm’s documentation
svprfb⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_s32offset⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_s64offset⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_u32base⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_u32base_offset⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_u32offset⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_u64base⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_u64base_offset⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_gather_u64offset⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfb_vnum⚠Experimental`sve`
  Prefetch bytes Arm’s documentation
svprfd⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_s32index⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_s64index⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_u32base⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_u32base_index⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_u32index⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_u64base⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_u64base_index⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_gather_u64index⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfd_vnum⚠Experimental`sve`
  Prefetch doublewords Arm’s documentation
svprfh⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_s32index⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_s64index⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_u32base⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_u32base_index⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_u32index⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_u64base⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_u64base_index⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_gather_u64index⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfh_vnum⚠Experimental`sve`
  Prefetch halfwords Arm’s documentation
svprfw⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_s32index⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_s64index⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_u32base⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_u32base_index⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_u32index⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_u64base⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_u64base_index⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_gather_u64index⚠Experimental`sve`
  Prefetch words Arm’s documentation
svprfw_vnum⚠Experimental`sve`
  Prefetch words Arm’s documentation
svptest_anyExperimental`sve`
  Test whether any active element is true Arm’s documentation
svptest_firstExperimental`sve`
  Test whether first active element is true Arm’s documentation
svptest_lastExperimental`sve`
  Test whether last active element is true Arm’s documentation
svptrue_b8Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_b16Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_b32Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_b64Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_pat_b8Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_pat_b16Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_pat_b32Experimental`sve`
  Set predicate elements to true Arm’s documentation
svptrue_pat_b64Experimental`sve`
  Set predicate elements to true Arm’s documentation
svqabs_s8_mExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s8_xExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s8_zExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s16_mExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s16_xExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s16_zExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s32_mExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s32_xExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s32_zExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s64_mExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s64_xExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqabs_s64_zExperimental`sve2` and `sve`
  Saturating absolute value Arm’s documentation
svqadd_n_s8Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_s8_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s8_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s8_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s16Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_s32Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_s64Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_s16_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s16_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s16_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s32_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s32_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s32_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s64_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s64_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_s64_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u8Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_u8_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u8_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u8_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u16Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_u32Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_u64Experimental`sve`
  Saturating add Arm’s documentation
svqadd_n_u16_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u16_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u16_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u32_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u32_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u32_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u64_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u64_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_n_u64_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s8Experimental`sve`
  Saturating add Arm’s documentation
svqadd_s8_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s8_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s8_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s16Experimental`sve`
  Saturating add Arm’s documentation
svqadd_s32Experimental`sve`
  Saturating add Arm’s documentation
svqadd_s64Experimental`sve`
  Saturating add Arm’s documentation
svqadd_s16_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s16_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s16_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s32_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s32_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s32_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s64_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s64_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_s64_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u8Experimental`sve`
  Saturating add Arm’s documentation
svqadd_u8_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u8_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u8_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u16Experimental`sve`
  Saturating add Arm’s documentation
svqadd_u32Experimental`sve`
  Saturating add Arm’s documentation
svqadd_u64Experimental`sve`
  Saturating add Arm’s documentation
svqadd_u16_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u16_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u16_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u32_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u32_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u32_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u64_mExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u64_xExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqadd_u64_zExperimental`sve2` and `sve`
  Saturating add Arm’s documentation
svqcadd_s8Experimental`sve2` and `sve`
  Saturating complex add with rotate Arm’s documentation
svqcadd_s16Experimental`sve2` and `sve`
  Saturating complex add with rotate Arm’s documentation
svqcadd_s32Experimental`sve2` and `sve`
  Saturating complex add with rotate Arm’s documentation
svqcadd_s64Experimental`sve2` and `sve`
  Saturating complex add with rotate Arm’s documentation
svqdecb_n_s32Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_n_s64Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_n_u32Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_n_u64Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_pat_n_s32Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_pat_n_s64Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_pat_n_u32Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecb_pat_n_u64Experimental`sve`
  Saturating decrement by number of byte elements Arm’s documentation
svqdecd_n_s32Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_n_s64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_n_u32Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_n_u64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_pat_n_s32Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_pat_n_s64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_pat_n_u32Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_pat_n_u64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_pat_s64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_pat_u64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_s64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdecd_u64Experimental`sve`
  Saturating decrement by number of doubleword elements Arm’s documentation
svqdech_n_s32Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_n_s64Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_n_u32Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_n_u64Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_pat_n_s32Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_pat_n_s64Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_pat_n_u32Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_pat_n_u64Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_pat_s16Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_pat_u16Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_s16Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdech_u16Experimental`sve`
  Saturating decrement by number of halfword elements Arm’s documentation
svqdecp_n_s32_b8Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s32_b16Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s32_b32Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s32_b64Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s64_b8Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s64_b16Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s64_b32Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_s64_b64Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u32_b8Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u32_b16Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u32_b32Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u32_b64Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u64_b8Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u64_b16Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u64_b32Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_n_u64_b64Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_s16Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_s32Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_s64Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_u16Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_u32Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecp_u64Experimental`sve`
  Saturating decrement by active element count Arm’s documentation
svqdecw_n_s32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_n_s64Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_n_u32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_n_u64Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_pat_n_s32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_pat_n_s64Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_pat_n_u32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_pat_n_u64Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_pat_s32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_pat_u32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_s32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdecw_u32Experimental`sve`
  Saturating decrement by number of word elements Arm’s documentation
svqdmlalb_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalb_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom) Arm’s documentation
svqdmlalbt_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom × top) Arm’s documentation
svqdmlalbt_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom × top) Arm’s documentation
svqdmlalbt_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom × top) Arm’s documentation
svqdmlalbt_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom × top) Arm’s documentation
svqdmlalbt_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom × top) Arm’s documentation
svqdmlalbt_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (bottom × top) Arm’s documentation
svqdmlalt_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlalt_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-add long (top) Arm’s documentation
svqdmlslb_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslb_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom) Arm’s documentation
svqdmlslbt_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation
svqdmlslbt_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation
svqdmlslbt_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation
svqdmlslbt_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation
svqdmlslbt_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation
svqdmlslbt_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (bottom × top) Arm’s documentation
svqdmlslt_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_s16Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_s32Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmlslt_s64Experimental`sve2` and `sve`
  Saturating doubling multiply-subtract long (top) Arm’s documentation
svqdmulh_lane_s16Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_n_s8Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_s8Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_s16Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_s32Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmulh_s64Experimental`sve2` and `sve`
  Saturating doubling multiply high Arm’s documentation
svqdmullb_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_s16Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_s32Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullb_s64Experimental`sve2` and `sve`
  Saturating doubling multiply long (bottom) Arm’s documentation
svqdmullt_lane_s32Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_lane_s64Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_n_s16Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_n_s32Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_n_s64Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_s16Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_s32Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqdmullt_s64Experimental`sve2` and `sve`
  Saturating doubling multiply long (top) Arm’s documentation
svqincb_n_s32Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_n_s64Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_n_u32Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_n_u64Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_pat_n_s32Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_pat_n_s64Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_pat_n_u32Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincb_pat_n_u64Experimental`sve`
  Saturating increment by number of byte elements Arm’s documentation
svqincd_n_s32Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_n_s64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_n_u32Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_n_u64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_pat_n_s32Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_pat_n_s64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_pat_n_u32Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_pat_n_u64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_pat_s64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_pat_u64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_s64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqincd_u64Experimental`sve`
  Saturating increment by number of doubleword elements Arm’s documentation
svqinch_n_s32Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_n_s64Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_n_u32Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_n_u64Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_pat_n_s32Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_pat_n_s64Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_pat_n_u32Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_pat_n_u64Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_pat_s16Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_pat_u16Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_s16Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqinch_u16Experimental`sve`
  Saturating increment by number of halfword elements Arm’s documentation
svqincp_n_s32_b8Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s32_b16Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s32_b32Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s32_b64Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s64_b8Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s64_b16Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s64_b32Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_s64_b64Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u32_b8Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u32_b16Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u32_b32Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u32_b64Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u64_b8Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u64_b16Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u64_b32Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_n_u64_b64Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_s16Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_s32Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_s64Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_u16Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_u32Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincp_u64Experimental`sve`
  Saturating increment by active element count Arm’s documentation
svqincw_n_s32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_n_s64Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_n_u32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_n_u64Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_pat_n_s32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_pat_n_s64Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_pat_n_u32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_pat_n_u64Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_pat_s32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_pat_u32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_s32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqincw_u32Experimental`sve`
  Saturating increment by number of word elements Arm’s documentation
svqneg_s8_mExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s8_xExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s8_zExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s16_mExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s16_xExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s16_zExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s32_mExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s32_xExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s32_zExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s64_mExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s64_xExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqneg_s64_zExperimental`sve2` and `sve`
  Saturating negate Arm’s documentation
svqrdcmlah_lane_s16Experimental`sve2` and `sve`
  Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation
svqrdcmlah_lane_s32Experimental`sve2` and `sve`
  Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation
svqrdcmlah_s8Experimental`sve2` and `sve`
  Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation
svqrdcmlah_s16Experimental`sve2` and `sve`
  Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation
svqrdcmlah_s32Experimental`sve2` and `sve`
  Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation
svqrdcmlah_s64Experimental`sve2` and `sve`
  Saturating rounding doubling complex multiply-add high with rotate Arm’s documentation
svqrdmlah_lane_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_lane_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_lane_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_n_s8Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_n_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_n_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_n_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_s8Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlah_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-add high Arm’s documentation
svqrdmlsh_lane_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_lane_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_lane_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_n_s8Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_n_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_n_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_n_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_s8Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmlsh_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply-subtract high Arm’s documentation
svqrdmulh_lane_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_lane_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_lane_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_n_s8Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_n_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_n_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_n_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_s8Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_s16Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_s32Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrdmulh_s64Experimental`sve2` and `sve`
  Saturating rounding doubling multiply high Arm’s documentation
svqrshl_n_s8_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s8_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s8_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s16_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s16_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s16_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s32_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s32_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s32_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s64_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s64_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_s64_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u8_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u8_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u8_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u16_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u16_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u16_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u32_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u32_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u32_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u64_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u64_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_n_u64_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s8_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s8_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s8_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s16_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s16_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s16_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s32_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s32_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s32_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s64_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s64_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_s64_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u8_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u8_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u8_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u16_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u16_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u16_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u32_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u32_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u32_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u64_mExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u64_xExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshl_u64_zExperimental`sve2` and `sve`
  Saturating rounding shift left Arm’s documentation
svqrshrnb_n_s16Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (bottom) Arm’s documentation
svqrshrnb_n_s32Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (bottom) Arm’s documentation
svqrshrnb_n_s64Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (bottom) Arm’s documentation
svqrshrnb_n_u16Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (bottom) Arm’s documentation
svqrshrnb_n_u32Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (bottom) Arm’s documentation
svqrshrnb_n_u64Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (bottom) Arm’s documentation
svqrshrnt_n_s16Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (top) Arm’s documentation
svqrshrnt_n_s32Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (top) Arm’s documentation
svqrshrnt_n_s64Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (top) Arm’s documentation
svqrshrnt_n_u16Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (top) Arm’s documentation
svqrshrnt_n_u32Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (top) Arm’s documentation
svqrshrnt_n_u64Experimental`sve2` and `sve`
  Saturating rounding shift right narrow (top) Arm’s documentation
svqrshrunb_n_s16Experimental`sve2` and `sve`
  Saturating rounding shift right unsigned narrow (bottom) Arm’s documentation
svqrshrunb_n_s32Experimental`sve2` and `sve`
  Saturating rounding shift right unsigned narrow (bottom) Arm’s documentation
svqrshrunb_n_s64Experimental`sve2` and `sve`
  Saturating rounding shift right unsigned narrow (bottom) Arm’s documentation
svqrshrunt_n_s16Experimental`sve2` and `sve`
  Saturating rounding shift right unsigned narrow (top) Arm’s documentation
svqrshrunt_n_s32Experimental`sve2` and `sve`
  Saturating rounding shift right unsigned narrow (top) Arm’s documentation
svqrshrunt_n_s64Experimental`sve2` and `sve`
  Saturating rounding shift right unsigned narrow (top) Arm’s documentation
svqshl_n_s8_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s8_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s8_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s16_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s16_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s16_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s32_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s32_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s32_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s64_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s64_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_s64_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u8_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u8_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u8_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u16_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u16_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u16_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u32_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u32_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u32_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u64_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u64_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_n_u64_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s8_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s8_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s8_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s16_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s16_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s16_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s32_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s32_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s32_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s64_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s64_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_s64_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u8_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u8_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u8_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u16_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u16_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u16_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u32_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u32_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u32_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u64_mExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u64_xExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshl_u64_zExperimental`sve2` and `sve`
  Saturating shift left Arm’s documentation
svqshlu_n_s8_mExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s8_xExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s8_zExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s16_mExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s16_xExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s16_zExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s32_mExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s32_xExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s32_zExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s64_mExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s64_xExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshlu_n_s64_zExperimental`sve2` and `sve`
  Saturating shift left unsigned Arm’s documentation
svqshrnb_n_s16Experimental`sve2` and `sve`
  Saturating shift right narrow (bottom) Arm’s documentation
svqshrnb_n_s32Experimental`sve2` and `sve`
  Saturating shift right narrow (bottom) Arm’s documentation
svqshrnb_n_s64Experimental`sve2` and `sve`
  Saturating shift right narrow (bottom) Arm’s documentation
svqshrnb_n_u16Experimental`sve2` and `sve`
  Saturating shift right narrow (bottom) Arm’s documentation
svqshrnb_n_u32Experimental`sve2` and `sve`
  Saturating shift right narrow (bottom) Arm’s documentation
svqshrnb_n_u64Experimental`sve2` and `sve`
  Saturating shift right narrow (bottom) Arm’s documentation
svqshrnt_n_s16Experimental`sve2` and `sve`
  Saturating shift right narrow (top) Arm’s documentation
svqshrnt_n_s32Experimental`sve2` and `sve`
  Saturating shift right narrow (top) Arm’s documentation
svqshrnt_n_s64Experimental`sve2` and `sve`
  Saturating shift right narrow (top) Arm’s documentation
svqshrnt_n_u16Experimental`sve2` and `sve`
  Saturating shift right narrow (top) Arm’s documentation
svqshrnt_n_u32Experimental`sve2` and `sve`
  Saturating shift right narrow (top) Arm’s documentation
svqshrnt_n_u64Experimental`sve2` and `sve`
  Saturating shift right narrow (top) Arm’s documentation
svqshrunb_n_s16Experimental`sve2` and `sve`
  Saturating shift right unsigned narrow (bottom) Arm’s documentation
svqshrunb_n_s32Experimental`sve2` and `sve`
  Saturating shift right unsigned narrow (bottom) Arm’s documentation
svqshrunb_n_s64Experimental`sve2` and `sve`
  Saturating shift right unsigned narrow (bottom) Arm’s documentation
svqshrunt_n_s16Experimental`sve2` and `sve`
  Saturating shift right unsigned narrow (top) Arm’s documentation
svqshrunt_n_s32Experimental`sve2` and `sve`
  Saturating shift right unsigned narrow (top) Arm’s documentation
svqshrunt_n_s64Experimental`sve2` and `sve`
  Saturating shift right unsigned narrow (top) Arm’s documentation
svqsub_n_s8Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_s8_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s8_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s8_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s16Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_s32Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_s64Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_s16_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s16_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s16_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s32_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s32_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s32_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s64_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s64_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_s64_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u8Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_u8_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u8_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u8_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u16Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_u32Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_u64Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_n_u16_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u16_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u16_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u32_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u32_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u32_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u64_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u64_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_n_u64_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s8Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_s8_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s8_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s8_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s16Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_s32Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_s64Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_s16_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s16_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s16_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s32_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s32_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s32_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s64_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s64_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_s64_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u8Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_u8_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u8_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u8_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u16Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_u32Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_u64Experimental`sve`
  Saturating subtract Arm’s documentation
svqsub_u16_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u16_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u16_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u32_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u32_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u32_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u64_mExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u64_xExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsub_u64_zExperimental`sve2` and `sve`
  Saturating subtract Arm’s documentation
svqsubr_n_s8_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s8_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s8_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s16_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s16_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s16_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s32_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s32_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s32_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s64_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s64_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_s64_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u8_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u8_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u8_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u16_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u16_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u16_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u32_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u32_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u32_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u64_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u64_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_n_u64_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s8_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s8_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s8_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s16_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s16_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s16_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s32_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s32_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s32_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s64_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s64_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_s64_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u8_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u8_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u8_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u16_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u16_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u16_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u32_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u32_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u32_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u64_mExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u64_xExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqsubr_u64_zExperimental`sve2` and `sve`
  Saturating subtract reversed Arm’s documentation
svqxtnb_s16Experimental`sve2` and `sve`
  Saturating extract narrow (bottom) Arm’s documentation
svqxtnb_s32Experimental`sve2` and `sve`
  Saturating extract narrow (bottom) Arm’s documentation
svqxtnb_s64Experimental`sve2` and `sve`
  Saturating extract narrow (bottom) Arm’s documentation
svqxtnb_u16Experimental`sve2` and `sve`
  Saturating extract narrow (bottom) Arm’s documentation
svqxtnb_u32Experimental`sve2` and `sve`
  Saturating extract narrow (bottom) Arm’s documentation
svqxtnb_u64Experimental`sve2` and `sve`
  Saturating extract narrow (bottom) Arm’s documentation
svqxtnt_s16Experimental`sve2` and `sve`
  Saturating extract narrow (top) Arm’s documentation
svqxtnt_s32Experimental`sve2` and `sve`
  Saturating extract narrow (top) Arm’s documentation
svqxtnt_s64Experimental`sve2` and `sve`
  Saturating extract narrow (top) Arm’s documentation
svqxtnt_u16Experimental`sve2` and `sve`
  Saturating extract narrow (top) Arm’s documentation
svqxtnt_u32Experimental`sve2` and `sve`
  Saturating extract narrow (top) Arm’s documentation
svqxtnt_u64Experimental`sve2` and `sve`
  Saturating extract narrow (top) Arm’s documentation
svqxtunb_s16Experimental`sve2` and `sve`
  Saturating extract unsigned narrow (bottom) Arm’s documentation
svqxtunb_s32Experimental`sve2` and `sve`
  Saturating extract unsigned narrow (bottom) Arm’s documentation
svqxtunb_s64Experimental`sve2` and `sve`
  Saturating extract unsigned narrow (bottom) Arm’s documentation
svqxtunt_s16Experimental`sve2` and `sve`
  Saturating extract unsigned narrow (top) Arm’s documentation
svqxtunt_s32Experimental`sve2` and `sve`
  Saturating extract unsigned narrow (top) Arm’s documentation
svqxtunt_s64Experimental`sve2` and `sve`
  Saturating extract unsigned narrow (top) Arm’s documentation
svraddhnb_n_s16Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_n_s32Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_n_s64Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_n_u16Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_n_u32Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_n_u64Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_s16Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_s32Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_s64Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_u16Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_u32Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnb_u64Experimental`sve2` and `sve`
  Rounding add narrow high part (bottom) Arm’s documentation
svraddhnt_n_s16Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_n_s32Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_n_s64Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_n_u16Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_n_u32Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_n_u64Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_s16Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_s32Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_s64Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_u16Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_u32Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svraddhnt_u64Experimental`sve2` and `sve`
  Rounding add narrow high part (top) Arm’s documentation
svrax1_s64Experimental`sve2-sha3` and `sve2` and `sve`
  Bitwise rotate left by 1 and exclusive OR Arm’s documentation
svrax1_u64Experimental`sve2-sha3` and `sve2` and `sve`
  Bitwise rotate left by 1 and exclusive OR Arm’s documentation
svrbit_s8_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s8_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s8_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s16_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s16_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s16_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s32_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s32_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s32_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s64_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s64_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_s64_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u8_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u8_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u8_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u16_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u16_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u16_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u32_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u32_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u32_zExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u64_mExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u64_xExperimental`sve`
  Reverse bits Arm’s documentation
svrbit_u64_zExperimental`sve`
  Reverse bits Arm’s documentation
svrdffrExperimental`sve`
  Read FFR, returning predicate of succesfully loaded elements Arm’s documentation
svrdffr_zExperimental`sve`
  Read FFR, returning predicate of succesfully loaded elements Arm’s documentation
svrecpe_f32Experimental`sve`
  Reciprocal estimate Arm’s documentation
svrecpe_f64Experimental`sve`
  Reciprocal estimate Arm’s documentation
svrecpe_u32_mExperimental`sve2` and `sve`
  Reciprocal estimate Arm’s documentation
svrecpe_u32_xExperimental`sve2` and `sve`
  Reciprocal estimate Arm’s documentation
svrecpe_u32_zExperimental`sve2` and `sve`
  Reciprocal estimate Arm’s documentation
svrecps_f32Experimental`sve`
  Reciprocal step Arm’s documentation
svrecps_f64Experimental`sve`
  Reciprocal step Arm’s documentation
svrecpx_f32_mExperimental`sve`
  Reciprocal exponent Arm’s documentation
svrecpx_f32_xExperimental`sve`
  Reciprocal exponent Arm’s documentation
svrecpx_f32_zExperimental`sve`
  Reciprocal exponent Arm’s documentation
svrecpx_f64_mExperimental`sve`
  Reciprocal exponent Arm’s documentation
svrecpx_f64_xExperimental`sve`
  Reciprocal exponent Arm’s documentation
svrecpx_f64_zExperimental`sve`
  Reciprocal exponent Arm’s documentation
svreinterpret_f32_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f32_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_f64_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s8_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s16_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s32_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_s64_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u8_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u16_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u32_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_f32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_f64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_s8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_s16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_s32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_s64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_u8Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_u16Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_u32Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svreinterpret_u64_u64Experimental`sve`
  Reinterpret vector contents Arm’s documentation
svrev_b8Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_b16Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_b32Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_b64Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_f32Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_f64Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_s8Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_s16Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_s32Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_s64Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_u8Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_u16Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_u32Experimental`sve`
  Reverse all elements Arm’s documentation
svrev_u64Experimental`sve`
  Reverse all elements Arm’s documentation
svrevb_s16_mExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s16_xExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s16_zExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s32_mExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s32_xExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s32_zExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s64_mExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s64_xExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_s64_zExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u16_mExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u16_xExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u16_zExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u32_mExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u32_xExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u32_zExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u64_mExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u64_xExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevb_u64_zExperimental`sve`
  Reverse bytes within elements Arm’s documentation
svrevh_s32_mExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_s32_xExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_s32_zExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_s64_mExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_s64_xExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_s64_zExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_u32_mExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_u32_xExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_u32_zExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_u64_mExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_u64_xExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevh_u64_zExperimental`sve`
  Reverse halfwords within elements Arm’s documentation
svrevw_s64_mExperimental`sve`
  Reverse words within elements Arm’s documentation
svrevw_s64_xExperimental`sve`
  Reverse words within elements Arm’s documentation
svrevw_s64_zExperimental`sve`
  Reverse words within elements Arm’s documentation
svrevw_u64_mExperimental`sve`
  Reverse words within elements Arm’s documentation
svrevw_u64_xExperimental`sve`
  Reverse words within elements Arm’s documentation
svrevw_u64_zExperimental`sve`
  Reverse words within elements Arm’s documentation
svrhadd_n_s8_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s8_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s8_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s16_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s16_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s16_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s32_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s32_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s32_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s64_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s64_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_s64_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u8_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u8_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u8_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u16_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u16_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u16_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u32_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u32_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u32_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u64_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u64_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_n_u64_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s8_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s8_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s8_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s16_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s16_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s16_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s32_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s32_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s32_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s64_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s64_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_s64_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u8_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u8_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u8_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u16_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u16_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u16_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u32_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u32_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u32_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u64_mExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u64_xExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrhadd_u64_zExperimental`sve2` and `sve`
  Rounding halving add Arm’s documentation
svrinta_f32_mExperimental`sve`
  Round to nearest, ties away from zero Arm’s documentation
svrinta_f32_xExperimental`sve`
  Round to nearest, ties away from zero Arm’s documentation
svrinta_f32_zExperimental`sve`
  Round to nearest, ties away from zero Arm’s documentation
svrinta_f64_mExperimental`sve`
  Round to nearest, ties away from zero Arm’s documentation
svrinta_f64_xExperimental`sve`
  Round to nearest, ties away from zero Arm’s documentation
svrinta_f64_zExperimental`sve`
  Round to nearest, ties away from zero Arm’s documentation
svrinti_f32_mExperimental`sve`
  Round using current rounding mode (inexact) Arm’s documentation
svrinti_f32_xExperimental`sve`
  Round using current rounding mode (inexact) Arm’s documentation
svrinti_f32_zExperimental`sve`
  Round using current rounding mode (inexact) Arm’s documentation
svrinti_f64_mExperimental`sve`
  Round using current rounding mode (inexact) Arm’s documentation
svrinti_f64_xExperimental`sve`
  Round using current rounding mode (inexact) Arm’s documentation
svrinti_f64_zExperimental`sve`
  Round using current rounding mode (inexact) Arm’s documentation
svrintm_f32_mExperimental`sve`
  Round towards -∞ Arm’s documentation
svrintm_f32_xExperimental`sve`
  Round towards -∞ Arm’s documentation
svrintm_f32_zExperimental`sve`
  Round towards -∞ Arm’s documentation
svrintm_f64_mExperimental`sve`
  Round towards -∞ Arm’s documentation
svrintm_f64_xExperimental`sve`
  Round towards -∞ Arm’s documentation
svrintm_f64_zExperimental`sve`
  Round towards -∞ Arm’s documentation
svrintn_f32_mExperimental`sve`
  Round to nearest, ties to even Arm’s documentation
svrintn_f32_xExperimental`sve`
  Round to nearest, ties to even Arm’s documentation
svrintn_f32_zExperimental`sve`
  Round to nearest, ties to even Arm’s documentation
svrintn_f64_mExperimental`sve`
  Round to nearest, ties to even Arm’s documentation
svrintn_f64_xExperimental`sve`
  Round to nearest, ties to even Arm’s documentation
svrintn_f64_zExperimental`sve`
  Round to nearest, ties to even Arm’s documentation
svrintp_f32_mExperimental`sve`
  Round towards +∞ Arm’s documentation
svrintp_f32_xExperimental`sve`
  Round towards +∞ Arm’s documentation
svrintp_f32_zExperimental`sve`
  Round towards +∞ Arm’s documentation
svrintp_f64_mExperimental`sve`
  Round towards +∞ Arm’s documentation
svrintp_f64_xExperimental`sve`
  Round towards +∞ Arm’s documentation
svrintp_f64_zExperimental`sve`
  Round towards +∞ Arm’s documentation
svrintx_f32_mExperimental`sve`
  Round using current rounding mode (exact) Arm’s documentation
svrintx_f32_xExperimental`sve`
  Round using current rounding mode (exact) Arm’s documentation
svrintx_f32_zExperimental`sve`
  Round using current rounding mode (exact) Arm’s documentation
svrintx_f64_mExperimental`sve`
  Round using current rounding mode (exact) Arm’s documentation
svrintx_f64_xExperimental`sve`
  Round using current rounding mode (exact) Arm’s documentation
svrintx_f64_zExperimental`sve`
  Round using current rounding mode (exact) Arm’s documentation
svrintz_f32_mExperimental`sve`
  Round towards zero Arm’s documentation
svrintz_f32_xExperimental`sve`
  Round towards zero Arm’s documentation
svrintz_f32_zExperimental`sve`
  Round towards zero Arm’s documentation
svrintz_f64_mExperimental`sve`
  Round towards zero Arm’s documentation
svrintz_f64_xExperimental`sve`
  Round towards zero Arm’s documentation
svrintz_f64_zExperimental`sve`
  Round towards zero Arm’s documentation
svrshl_n_s8_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s8_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s8_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s16_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s16_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s16_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s32_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s32_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s32_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s64_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s64_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_s64_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u8_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u8_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u8_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u16_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u16_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u16_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u32_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u32_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u32_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u64_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u64_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_n_u64_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s8_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s8_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s8_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s16_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s16_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s16_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s32_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s32_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s32_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s64_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s64_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_s64_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u8_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u8_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u8_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u16_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u16_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u16_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u32_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u32_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u32_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u64_mExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u64_xExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshl_u64_zExperimental`sve2` and `sve`
  Rounding shift left Arm’s documentation
svrshr_n_s8_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s8_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s8_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s16_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s16_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s16_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s32_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s32_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s32_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s64_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s64_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_s64_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u8_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u8_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u8_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u16_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u16_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u16_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u32_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u32_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u32_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u64_mExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u64_xExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshr_n_u64_zExperimental`sve2` and `sve`
  Rounding shift right Arm’s documentation
svrshrnb_n_s16Experimental`sve2` and `sve`
  Rounding shift right narrow (bottom) Arm’s documentation
svrshrnb_n_s32Experimental`sve2` and `sve`
  Rounding shift right narrow (bottom) Arm’s documentation
svrshrnb_n_s64Experimental`sve2` and `sve`
  Rounding shift right narrow (bottom) Arm’s documentation
svrshrnb_n_u16Experimental`sve2` and `sve`
  Rounding shift right narrow (bottom) Arm’s documentation
svrshrnb_n_u32Experimental`sve2` and `sve`
  Rounding shift right narrow (bottom) Arm’s documentation
svrshrnb_n_u64Experimental`sve2` and `sve`
  Rounding shift right narrow (bottom) Arm’s documentation
svrshrnt_n_s16Experimental`sve2` and `sve`
  Rounding shift right narrow (top) Arm’s documentation
svrshrnt_n_s32Experimental`sve2` and `sve`
  Rounding shift right narrow (top) Arm’s documentation
svrshrnt_n_s64Experimental`sve2` and `sve`
  Rounding shift right narrow (top) Arm’s documentation
svrshrnt_n_u16Experimental`sve2` and `sve`
  Rounding shift right narrow (top) Arm’s documentation
svrshrnt_n_u32Experimental`sve2` and `sve`
  Rounding shift right narrow (top) Arm’s documentation
svrshrnt_n_u64Experimental`sve2` and `sve`
  Rounding shift right narrow (top) Arm’s documentation
svrsqrte_f32Experimental`sve`
  Reciprocal square root estimate Arm’s documentation
svrsqrte_f64Experimental`sve`
  Reciprocal square root estimate Arm’s documentation
svrsqrte_u32_mExperimental`sve2` and `sve`
  Reciprocal square root estimate Arm’s documentation
svrsqrte_u32_xExperimental`sve2` and `sve`
  Reciprocal square root estimate Arm’s documentation
svrsqrte_u32_zExperimental`sve2` and `sve`
  Reciprocal square root estimate Arm’s documentation
svrsqrts_f32Experimental`sve`
  Reciprocal square root step Arm’s documentation
svrsqrts_f64Experimental`sve`
  Reciprocal square root step Arm’s documentation
svrsra_n_s8Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_s16Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_s32Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_s64Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_u8Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_u16Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_u32Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsra_n_u64Experimental`sve2` and `sve`
  Rounding shift right and accumulate Arm’s documentation
svrsubhnb_n_s16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_n_s32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_n_s64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_n_u16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_n_u32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_n_u64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_s16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_s32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_s64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_u16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_u32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnb_u64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (bottom) Arm’s documentation
svrsubhnt_n_s16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_n_s32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_n_s64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_n_u16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_n_u32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_n_u64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_s16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_s32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_s64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_u16Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_u32Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svrsubhnt_u64Experimental`sve2` and `sve`
  Rounding subtract narrow high part (top) Arm’s documentation
svsbclb_n_u32Experimental`sve2` and `sve`
  Subtract with borrow long (bottom) Arm’s documentation
svsbclb_n_u64Experimental`sve2` and `sve`
  Subtract with borrow long (bottom) Arm’s documentation
svsbclb_u32Experimental`sve2` and `sve`
  Subtract with borrow long (bottom) Arm’s documentation
svsbclb_u64Experimental`sve2` and `sve`
  Subtract with borrow long (bottom) Arm’s documentation
svsbclt_n_u32Experimental`sve2` and `sve`
  Subtract with borrow long (top) Arm’s documentation
svsbclt_n_u64Experimental`sve2` and `sve`
  Subtract with borrow long (top) Arm’s documentation
svsbclt_u32Experimental`sve2` and `sve`
  Subtract with borrow long (top) Arm’s documentation
svsbclt_u64Experimental`sve2` and `sve`
  Subtract with borrow long (top) Arm’s documentation
svscale_f32_mExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_f32_xExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_f32_zExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_f64_mExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_f64_xExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_f64_zExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_n_f32_mExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_n_f32_xExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_n_f32_zExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_n_f64_mExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_n_f64_xExperimental`sve`
  Adjust exponent Arm’s documentation
svscale_n_f64_zExperimental`sve`
  Adjust exponent Arm’s documentation
svsel_bExperimental`sve`
  Conditionally select elements Arm’s documentation
svsel_f32Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_f64Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_s8Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_s16Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_s32Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_s64Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_u8Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_u16Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_u32Experimental`sve`
  Conditionally select elements Arm’s documentation
svsel_u64Experimental`sve`
  Conditionally select elements Arm’s documentation
svset2_f32Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_f64Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_s8Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_s16Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_s32Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_s64Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_u8Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_u16Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_u32Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset2_u64Experimental`sve`
  Change one vector in a tuple of two vectors Arm’s documentation
svset3_f32Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_f64Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_s8Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_s16Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_s32Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_s64Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_u8Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_u16Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_u32Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset3_u64Experimental`sve`
  Change one vector in a tuple of three vectors Arm’s documentation
svset4_f32Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_f64Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_s8Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_s16Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_s32Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_s64Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_u8Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_u16Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_u32Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svset4_u64Experimental`sve`
  Change one vector in a tuple of four vectors Arm’s documentation
svsetffrExperimental`sve`
  Initialize the first-fault register to all-true Arm’s documentation
svshllb_n_s16Experimental`sve2` and `sve`
  Shift left long (bottom) Arm’s documentation
svshllb_n_s32Experimental`sve2` and `sve`
  Shift left long (bottom) Arm’s documentation
svshllb_n_s64Experimental`sve2` and `sve`
  Shift left long (bottom) Arm’s documentation
svshllb_n_u16Experimental`sve2` and `sve`
  Shift left long (bottom) Arm’s documentation
svshllb_n_u32Experimental`sve2` and `sve`
  Shift left long (bottom) Arm’s documentation
svshllb_n_u64Experimental`sve2` and `sve`
  Shift left long (bottom) Arm’s documentation
svshllt_n_s16Experimental`sve2` and `sve`
  Shift left long (top) Arm’s documentation
svshllt_n_s32Experimental`sve2` and `sve`
  Shift left long (top) Arm’s documentation
svshllt_n_s64Experimental`sve2` and `sve`
  Shift left long (top) Arm’s documentation
svshllt_n_u16Experimental`sve2` and `sve`
  Shift left long (top) Arm’s documentation
svshllt_n_u32Experimental`sve2` and `sve`
  Shift left long (top) Arm’s documentation
svshllt_n_u64Experimental`sve2` and `sve`
  Shift left long (top) Arm’s documentation
svshrnb_n_s16Experimental`sve2` and `sve`
  Shift right narrow (bottom) Arm’s documentation
svshrnb_n_s32Experimental`sve2` and `sve`
  Shift right narrow (bottom) Arm’s documentation
svshrnb_n_s64Experimental`sve2` and `sve`
  Shift right narrow (bottom) Arm’s documentation
svshrnb_n_u16Experimental`sve2` and `sve`
  Shift right narrow (bottom) Arm’s documentation
svshrnb_n_u32Experimental`sve2` and `sve`
  Shift right narrow (bottom) Arm’s documentation
svshrnb_n_u64Experimental`sve2` and `sve`
  Shift right narrow (bottom) Arm’s documentation
svshrnt_n_s16Experimental`sve2` and `sve`
  Shift right narrow (top) Arm’s documentation
svshrnt_n_s32Experimental`sve2` and `sve`
  Shift right narrow (top) Arm’s documentation
svshrnt_n_s64Experimental`sve2` and `sve`
  Shift right narrow (top) Arm’s documentation
svshrnt_n_u16Experimental`sve2` and `sve`
  Shift right narrow (top) Arm’s documentation
svshrnt_n_u32Experimental`sve2` and `sve`
  Shift right narrow (top) Arm’s documentation
svshrnt_n_u64Experimental`sve2` and `sve`
  Shift right narrow (top) Arm’s documentation
svsli_n_s8Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_s16Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_s32Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_s64Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_u8Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_u16Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_u32Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsli_n_u64Experimental`sve2` and `sve`
  Shift left and insert Arm’s documentation
svsm4e_u32Experimental`sve2-sm4` and `sve2` and `sve`
  SM4 encryption and decryption Arm’s documentation
svsm4ekey_u32Experimental`sve2-sm4` and `sve2` and `sve`
  SM4 key updates Arm’s documentation
svsplice_f32Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_f64Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_s8Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_s16Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_s32Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_s64Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_u8Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_u16Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_u32Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsplice_u64Experimental`sve`
  Splice two vectors under predicate control Arm’s documentation
svsqadd_n_u8_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u8_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u8_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u16_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u16_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u16_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u32_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u32_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u32_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u64_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u64_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_n_u64_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u8_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u8_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u8_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u16_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u16_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u16_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u32_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u32_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u32_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u64_mExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u64_xExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqadd_u64_zExperimental`sve2` and `sve`
  Saturating add with signed addend Arm’s documentation
svsqrt_f32_mExperimental`sve`
  Square root Arm’s documentation
svsqrt_f32_xExperimental`sve`
  Square root Arm’s documentation
svsqrt_f32_zExperimental`sve`
  Square root Arm’s documentation
svsqrt_f64_mExperimental`sve`
  Square root Arm’s documentation
svsqrt_f64_xExperimental`sve`
  Square root Arm’s documentation
svsqrt_f64_zExperimental`sve`
  Square root Arm’s documentation
svsra_n_s8Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_s16Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_s32Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_s64Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_u8Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_u16Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_u32Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsra_n_u64Experimental`sve2` and `sve`
  Shift right and accumulate Arm’s documentation
svsri_n_s8Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_s16Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_s32Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_s64Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_u8Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_u16Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_u32Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svsri_n_u64Experimental`sve2` and `sve`
  Shift right and insert Arm’s documentation
svst1_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_s8⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_s16⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s32index_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s32index_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s32index_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s32offset_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s32offset_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s32offset_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s64index_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s64index_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s64index_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s64offset_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s64offset_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_s64offset_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_index_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_index_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_index_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_offset_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_offset_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_offset_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32base_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32index_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32index_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32index_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32offset_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32offset_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u32offset_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_index_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_index_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_index_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_offset_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_offset_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_offset_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64base_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64index_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64index_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64index_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64offset_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64offset_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_scatter_u64offset_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_u8⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_u16⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_f32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_f64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_s8⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_s16⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_s32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_s64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_u8⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_u16⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_u32⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1_vnum_u64⚠Experimental`sve`
  Non-truncating store Arm’s documentation
svst1b_s16⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_s32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_s64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_s32offset_s32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_s32offset_u32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_s64offset_s64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_s64offset_u64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u32base_offset_s32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u32base_offset_u32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u32base_s32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u32base_u32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u32offset_s32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u32offset_u32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u64base_offset_s64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u64base_offset_u64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u64base_s64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u64base_u64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u64offset_s64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_scatter_u64offset_u64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_u16⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_u32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_u64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_vnum_s16⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_vnum_s32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_vnum_s64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_vnum_u16⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_vnum_u32⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1b_vnum_u64⚠Experimental`sve`
  Truncate to 8 bits and store Arm’s documentation
svst1h_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s32index_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s32index_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s32offset_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s32offset_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s64index_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s64index_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s64offset_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_s64offset_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32base_index_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32base_index_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32base_offset_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32base_offset_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32base_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32base_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32index_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32index_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32offset_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u32offset_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64base_index_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64base_index_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64base_offset_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64base_offset_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64base_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64base_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64index_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64index_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64offset_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_scatter_u64offset_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_vnum_s32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_vnum_s64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_vnum_u32⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1h_vnum_u64⚠Experimental`sve`
  Truncate to 16 bits and store Arm’s documentation
svst1w_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_s64index_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_s64index_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_s64offset_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_s64offset_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64base_index_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64base_index_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64base_offset_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64base_offset_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64base_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64base_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64index_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64index_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64offset_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_scatter_u64offset_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_vnum_s64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst1w_vnum_u64⚠Experimental`sve`
  Truncate to 32 bits and store Arm’s documentation
svst2_f32⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_f64⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_s8⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_s16⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_s32⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_s64⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_u8⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_u16⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_u32⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_u64⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_f32⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_f64⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_s8⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_s16⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_s32⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_s64⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_u8⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_u16⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_u32⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst2_vnum_u64⚠Experimental`sve`
  Store two vectors into two-element tuples Arm’s documentation
svst3_f32⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_f64⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_s8⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_s16⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_s32⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_s64⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_u8⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_u16⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_u32⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_u64⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_f32⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_f64⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_s8⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_s16⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_s32⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_s64⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_u8⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_u16⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_u32⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst3_vnum_u64⚠Experimental`sve`
  Store three vectors into three-element tuples Arm’s documentation
svst4_f32⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_f64⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_s8⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_s16⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_s32⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_s64⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_u8⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_u16⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_u32⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_u64⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_f32⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_f64⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_s8⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_s16⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_s32⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_s64⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_u8⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_u16⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_u32⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svst4_vnum_u64⚠Experimental`sve`
  Store four vectors into four-element tuples Arm’s documentation
svstnt1_f32⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_f64⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_s8⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_s16⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_s32⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_s64⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_s64index_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_s64index_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_s64index_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_s64offset_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_s64offset_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_s64offset_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_f32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_index_f32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_index_s32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_index_u32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_offset_f32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_s32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32base_u32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32offset_f32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32offset_s32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u32offset_u32⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_index_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_index_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_index_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_offset_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64base_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64index_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64index_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64index_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64offset_f64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64offset_s64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_scatter_u64offset_u64⚠Experimental`sve2` and `sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_u8⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_u16⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_u32⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_u64⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_f32⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_f64⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_s8⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_s16⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_s32⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_s64⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_u8⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_u16⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_u32⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1_vnum_u64⚠Experimental`sve`
  Non-truncating store, non-temporal Arm’s documentation
svstnt1b_scatter_s64offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_s64offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u32base_s32⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u32base_u32⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u32offset_s32⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u32offset_u32⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u64base_s64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u64base_u64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u64offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1b_scatter_u64offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 8 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_s64index_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_s64index_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_s64offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_s64offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32base_index_s32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32base_index_u32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32base_offset_s32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32base_offset_u32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32base_s32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32base_u32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32offset_s32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u32offset_u32⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64base_index_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64base_index_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64base_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64base_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64index_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64index_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1h_scatter_u64offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 16 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_s64index_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_s64index_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_s64offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_s64offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64base_index_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64base_index_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64base_offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64base_offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64base_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64base_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64index_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64index_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64offset_s64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svstnt1w_scatter_u64offset_u64⚠Experimental`sve2` and `sve`
  Truncate to 32 bits and store, non-temporal Arm’s documentation
svsub_f32_mExperimental`sve`
  Subtract Arm’s documentation
svsub_f32_xExperimental`sve`
  Subtract Arm’s documentation
svsub_f32_zExperimental`sve`
  Subtract Arm’s documentation
svsub_f64_mExperimental`sve`
  Subtract Arm’s documentation
svsub_f64_xExperimental`sve`
  Subtract Arm’s documentation
svsub_f64_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_f32_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_f32_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_f32_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_f64_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_f64_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_f64_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s8_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s8_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s8_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s16_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s16_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s16_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s32_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s32_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s32_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s64_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s64_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_s64_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u8_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u8_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u8_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u16_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u16_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u16_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u32_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u32_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u32_zExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u64_mExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u64_xExperimental`sve`
  Subtract Arm’s documentation
svsub_n_u64_zExperimental`sve`
  Subtract Arm’s documentation
svsub_s8_mExperimental`sve`
  Subtract Arm’s documentation
svsub_s8_xExperimental`sve`
  Subtract Arm’s documentation
svsub_s8_zExperimental`sve`
  Subtract Arm’s documentation
svsub_s16_mExperimental`sve`
  Subtract Arm’s documentation
svsub_s16_xExperimental`sve`
  Subtract Arm’s documentation
svsub_s16_zExperimental`sve`
  Subtract Arm’s documentation
svsub_s32_mExperimental`sve`
  Subtract Arm’s documentation
svsub_s32_xExperimental`sve`
  Subtract Arm’s documentation
svsub_s32_zExperimental`sve`
  Subtract Arm’s documentation
svsub_s64_mExperimental`sve`
  Subtract Arm’s documentation
svsub_s64_xExperimental`sve`
  Subtract Arm’s documentation
svsub_s64_zExperimental`sve`
  Subtract Arm’s documentation
svsub_u8_mExperimental`sve`
  Subtract Arm’s documentation
svsub_u8_xExperimental`sve`
  Subtract Arm’s documentation
svsub_u8_zExperimental`sve`
  Subtract Arm’s documentation
svsub_u16_mExperimental`sve`
  Subtract Arm’s documentation
svsub_u16_xExperimental`sve`
  Subtract Arm’s documentation
svsub_u16_zExperimental`sve`
  Subtract Arm’s documentation
svsub_u32_mExperimental`sve`
  Subtract Arm’s documentation
svsub_u32_xExperimental`sve`
  Subtract Arm’s documentation
svsub_u32_zExperimental`sve`
  Subtract Arm’s documentation
svsub_u64_mExperimental`sve`
  Subtract Arm’s documentation
svsub_u64_xExperimental`sve`
  Subtract Arm’s documentation
svsub_u64_zExperimental`sve`
  Subtract Arm’s documentation
svsubhnb_n_s16Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_n_s32Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_n_s64Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_n_u16Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_n_u32Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_n_u64Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_s16Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_s32Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_s64Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_u16Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_u32Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnb_u64Experimental`sve2` and `sve`
  Subtract narrow high part (bottom) Arm’s documentation
svsubhnt_n_s16Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_n_s32Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_n_s64Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_n_u16Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_n_u32Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_n_u64Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_s16Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_s32Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_s64Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_u16Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_u32Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsubhnt_u64Experimental`sve2` and `sve`
  Subtract narrow high part (top) Arm’s documentation
svsublb_n_s16Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_n_s32Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_n_s64Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_n_u16Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_n_u32Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_n_u64Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_s16Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_s32Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_s64Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_u16Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_u32Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublb_u64Experimental`sve2` and `sve`
  Subtract long (bottom) Arm’s documentation
svsublbt_n_s16Experimental`sve2` and `sve`
  Subtract long (bottom - top) Arm’s documentation
svsublbt_n_s32Experimental`sve2` and `sve`
  Subtract long (bottom - top) Arm’s documentation
svsublbt_n_s64Experimental`sve2` and `sve`
  Subtract long (bottom - top) Arm’s documentation
svsublbt_s16Experimental`sve2` and `sve`
  Subtract long (bottom - top) Arm’s documentation
svsublbt_s32Experimental`sve2` and `sve`
  Subtract long (bottom - top) Arm’s documentation
svsublbt_s64Experimental`sve2` and `sve`
  Subtract long (bottom - top) Arm’s documentation
svsublt_n_s16Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_n_s32Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_n_s64Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_n_u16Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_n_u32Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_n_u64Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_s16Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_s32Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_s64Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_u16Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_u32Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsublt_u64Experimental`sve2` and `sve`
  Subtract long (top) Arm’s documentation
svsubltb_n_s16Experimental`sve2` and `sve`
  Subtract long (top - bottom) Arm’s documentation
svsubltb_n_s32Experimental`sve2` and `sve`
  Subtract long (top - bottom) Arm’s documentation
svsubltb_n_s64Experimental`sve2` and `sve`
  Subtract long (top - bottom) Arm’s documentation
svsubltb_s16Experimental`sve2` and `sve`
  Subtract long (top - bottom) Arm’s documentation
svsubltb_s32Experimental`sve2` and `sve`
  Subtract long (top - bottom) Arm’s documentation
svsubltb_s64Experimental`sve2` and `sve`
  Subtract long (top - bottom) Arm’s documentation
svsubr_f32_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_f32_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_f32_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_f64_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_f64_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_f64_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_f32_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_f32_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_f32_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_f64_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_f64_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_f64_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s8_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s8_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s8_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s16_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s16_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s16_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s32_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s32_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s32_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s64_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s64_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_s64_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u8_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u8_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u8_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u16_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u16_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u16_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u32_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u32_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u32_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u64_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u64_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_n_u64_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s8_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s8_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s8_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s16_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s16_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s16_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s32_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s32_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s32_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s64_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s64_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_s64_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u8_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u8_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u8_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u16_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u16_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u16_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u32_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u32_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u32_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u64_mExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u64_xExperimental`sve`
  Subtract reversed Arm’s documentation
svsubr_u64_zExperimental`sve`
  Subtract reversed Arm’s documentation
svsubwb_n_s16Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_n_s32Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_n_s64Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_n_u16Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_n_u32Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_n_u64Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_s16Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_s32Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_s64Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_u16Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_u32Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwb_u64Experimental`sve2` and `sve`
  Subtract wide (bottom) Arm’s documentation
svsubwt_n_s16Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_n_s32Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_n_s64Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_n_u16Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_n_u32Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_n_u64Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_s16Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_s32Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_s64Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_u16Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_u32Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsubwt_u64Experimental`sve2` and `sve`
  Subtract wide (top) Arm’s documentation
svsudot_lane_s32Experimental`i8mm` and `sve`
  Dot product (signed × unsigned) Arm’s documentation
svsudot_n_s32Experimental`i8mm` and `sve`
  Dot product (signed × unsigned) Arm’s documentation
svsudot_s32Experimental`i8mm` and `sve`
  Dot product (signed × unsigned) Arm’s documentation
svtbl2_f32Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_f64Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_s8Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_s16Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_s32Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_s64Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_u8Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_u16Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_u32Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl2_u64Experimental`sve2` and `sve`
  Table lookup in two-vector table Arm’s documentation
svtbl_f32Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_f64Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_s8Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_s16Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_s32Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_s64Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_u8Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_u16Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_u32Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbl_u64Experimental`sve`
  Table lookup in single-vector table Arm’s documentation
svtbx_f32Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_f64Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_s8Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_s16Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_s32Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_s64Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_u8Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_u16Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_u32Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtbx_u64Experimental`sve2` and `sve`
  Table lookup in single-vector table (merging) Arm’s documentation
svtmad_f32Experimental`sve`
  Trigonometric multiply-add coefficient Arm’s documentation
svtmad_f64Experimental`sve`
  Trigonometric multiply-add coefficient Arm’s documentation
svtrn1_b8Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_b16Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_b32Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_b64Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_f32Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_f64Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_s8Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_s16Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_s32Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_s64Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_u8Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_u16Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_u32Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1_u64Experimental`sve`
  Interleave even elements from two inputs Arm’s documentation
svtrn1q_f32Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_f64Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_s8Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_s16Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_s32Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_s64Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_u8Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_u16Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_u32Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn1q_u64Experimental`f64mm` and `sve`
  Interleave even quadwords from two inputs Arm’s documentation
svtrn2_b8Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_b16Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_b32Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_b64Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_f32Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_f64Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_s8Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_s16Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_s32Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_s64Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_u8Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_u16Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_u32Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2_u64Experimental`sve`
  Interleave odd elements from two inputs Arm’s documentation
svtrn2q_f32Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_f64Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_s8Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_s16Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_s32Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_s64Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_u8Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_u16Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_u32Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtrn2q_u64Experimental`f64mm` and `sve`
  Interleave odd quadwords from two inputs Arm’s documentation
svtsmul_f32Experimental`sve`
  Trigonometric starting value Arm’s documentation
svtsmul_f64Experimental`sve`
  Trigonometric starting value Arm’s documentation
svtssel_f32Experimental`sve`
  Trigonometric select coefficient Arm’s documentation
svtssel_f64Experimental`sve`
  Trigonometric select coefficient Arm’s documentation
svundef2_f32⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_f64⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_s8⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_s16⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_s32⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_s64⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_u8⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_u16⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_u32⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef2_u64⚠Experimental`sve`
  Create an uninitialized tuple of two vectors Arm’s documentation
svundef3_f32⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_f64⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_s8⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_s16⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_s32⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_s64⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_u8⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_u16⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_u32⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef3_u64⚠Experimental`sve`
  Create an uninitialized tuple of three vectors Arm’s documentation
svundef4_f32⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_f64⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_s8⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_s16⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_s32⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_s64⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_u8⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_u16⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_u32⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef4_u64⚠Experimental`sve`
  Create an uninitialized tuple of four vectors Arm’s documentation
svundef_f32⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_f64⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_s8⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_s16⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_s32⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_s64⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_u8⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_u16⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_u32⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svundef_u64⚠Experimental`sve`
  Create an uninitialized vector Arm’s documentation
svunpkhi_bExperimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpkhi_s16Experimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpkhi_s32Experimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpkhi_s64Experimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpkhi_u16Experimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpkhi_u32Experimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpkhi_u64Experimental`sve2` and `sve`
  Unpack and extend high half Arm’s documentation
svunpklo_bExperimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svunpklo_s16Experimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svunpklo_s32Experimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svunpklo_s64Experimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svunpklo_u16Experimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svunpklo_u32Experimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svunpklo_u64Experimental`sve2` and `sve`
  Unpack and extend low half Arm’s documentation
svuqadd_n_s8_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s8_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s8_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s16_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s16_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s16_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s32_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s32_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s32_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s64_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s64_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_n_s64_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s8_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s8_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s8_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s16_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s16_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s16_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s32_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s32_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s32_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s64_mExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s64_xExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svuqadd_s64_zExperimental`sve2` and `sve`
  Saturating add with unsigned addend Arm’s documentation
svusdot_lane_s32Experimental`i8mm` and `sve`
  Dot product (unsigned × signed) Arm’s documentation
svusdot_n_s32Experimental`i8mm` and `sve`
  Dot product (unsigned × signed) Arm’s documentation
svusdot_s32Experimental`i8mm` and `sve`
  Dot product (unsigned × signed) Arm’s documentation
svusmmla_s32Experimental`i8mm` and `sve`
  Matrix multiply-accumulate (unsigned × signed) Arm’s documentation
svuzp1_b8Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_b16Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_b32Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_b64Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_f32Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_f64Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_s8Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_s16Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_s32Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_s64Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_u8Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_u16Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_u32Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1_u64Experimental`sve`
  Concatenate even elements from two inputs Arm’s documentation
svuzp1q_f32Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_f64Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_s8Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_s16Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_s32Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_s64Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_u8Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_u16Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_u32Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp1q_u64Experimental`f64mm` and `sve`
  Concatenate even quadwords from two inputs Arm’s documentation
svuzp2_b8Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_b16Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_b32Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_b64Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_f32Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_f64Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_s8Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_s16Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_s32Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_s64Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_u8Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_u16Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_u32Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2_u64Experimental`sve`
  Concatenate odd elements from two inputs Arm’s documentation
svuzp2q_f32Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_f64Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_s8Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_s16Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_s32Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_s64Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_u8Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_u16Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_u32Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svuzp2q_u64Experimental`f64mm` and `sve`
  Concatenate odd quadwords from two inputs Arm’s documentation
svwhilege_b8_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b8_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b8_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b8_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b16_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b16_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b16_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b16_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b32_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b32_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b32_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b32_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b64_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b64_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b64_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilege_b64_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than or equal to Arm’s documentation
svwhilegt_b8_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b8_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b8_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b8_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b16_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b16_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b16_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b16_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b32_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b32_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b32_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b32_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b64_s32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b64_s64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b64_u32Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilegt_b64_u64Experimental`sve2` and `sve`
  While decrementing scalar is greater than Arm’s documentation
svwhilele_b8_s32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b8_s64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b8_u32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b8_u64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b16_s32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b16_s64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b16_u32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b16_u64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b32_s32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b32_s64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b32_u32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b32_u64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b64_s32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b64_s64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b64_u32Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilele_b64_u64Experimental`sve`
  While incrementing scalar is less than or equal to Arm’s documentation
svwhilelt_b8_s32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b8_s64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b8_u32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b8_u64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b16_s32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b16_s64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b16_u32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b16_u64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b32_s32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b32_s64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b32_u32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b32_u64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b64_s32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b64_s64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b64_u32Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilelt_b64_u64Experimental`sve`
  While incrementing scalar is less than Arm’s documentation
svwhilerw_f32⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_f64⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_s8⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_s16⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_s32⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_s64⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_u8⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_u16⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_u32⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilerw_u64⚠Experimental`sve2` and `sve`
  While free of read-after-write conflicts Arm’s documentation
svwhilewr_f32⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_f64⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_s8⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_s16⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_s32⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_s64⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_u8⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_u16⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_u32⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwhilewr_u64⚠Experimental`sve2` and `sve`
  While free of write-after-read conflicts Arm’s documentation
svwrffrExperimental`sve`
  Write to the first-fault register Arm’s documentation
svxar_n_s8Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_s16Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_s32Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_s64Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_u8Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_u16Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_u32Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svxar_n_u64Experimental`sve2` and `sve`
  Bitwise exclusive OR and rotate right Arm’s documentation
svzip1_b8Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_b16Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_b32Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_b64Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_f32Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_f64Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_s8Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_s16Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_s32Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_s64Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_u8Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_u16Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_u32Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1_u64Experimental`sve`
  Interleave elements from low halves of two inputs Arm’s documentation
svzip1q_f32Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_f64Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_s8Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_s16Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_s32Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_s64Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_u8Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_u16Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_u32Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip1q_u64Experimental`f64mm` and `sve`
  Interleave quadwords from low halves of two inputs Arm’s documentation
svzip2_b8Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_b16Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_b32Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_b64Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_f32Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_f64Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_s8Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_s16Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_s32Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_s64Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_u8Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_u16Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_u32Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2_u64Experimental`sve`
  Interleave elements from high halves of two inputs Arm’s documentation
svzip2q_f32Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_f64Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_s8Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_s16Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_s32Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_s64Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_u8Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_u16Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_u32Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
svzip2q_u64Experimental`f64mm` and `sve`
  Interleave quadwords from high halves of two inputs Arm’s documentation
vabdh_f16Experimental`fp16` and `neon`
  Floating-point absolute difference Arm’s documentation
vabsh_f16Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Floating-point absolute value Arm’s documentation
vaddh_f16Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Add Arm’s documentation
vamax_f16Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute maximum Arm’s documentation
vamax_f32Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute maximum Arm’s documentation
vamaxq_f16Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute maximum Arm’s documentation
vamaxq_f32Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute maximum Arm’s documentation
vamaxq_f64Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute maximum Arm’s documentation
vamin_f16Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute minimum Arm’s documentation
vamin_f32Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute minimum Arm’s documentation
vaminq_f16Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute minimum Arm’s documentation
vaminq_f32Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute minimum Arm’s documentation
vaminq_f64Experimental`faminmax` and `neon`
  Multi-vector floating-point absolute minimum Arm’s documentation
vcadd_rot90_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex add Arm’s documentation
vcadd_rot90_f32Experimental`fcma` and `neon`
  Floating-point complex add Arm’s documentation
vcadd_rot270_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex add Arm’s documentation
vcadd_rot270_f32Experimental`fcma` and `neon`
  Floating-point complex add Arm’s documentation
vcaddq_rot90_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex add Arm’s documentation
vcaddq_rot90_f32Experimental`fcma` and `neon`
  Floating-point complex add Arm’s documentation
vcaddq_rot90_f64Experimental`fcma` and `neon`
  Floating-point complex add Arm’s documentation
vcaddq_rot270_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex add Arm’s documentation
vcaddq_rot270_f32Experimental`fcma` and `neon`
  Floating-point complex add Arm’s documentation
vcaddq_rot270_f64Experimental`fcma` and `neon`
  Floating-point complex add Arm’s documentation
vcageh_f16Experimental`fp16` and `neon`
  Floating-point absolute compare greater than or equal Arm’s documentation
vcagth_f16Experimental`fp16` and `neon`
  Floating-point absolute compare greater than Arm’s documentation
vcaleh_f16Experimental`fp16` and `neon`
  Floating-point absolute compare less than or equal Arm’s documentation
vcalth_f16Experimental`fp16` and `neon`
  Floating-point absolute compare less than Arm’s documentation
vceqh_f16Experimental`fp16` and `neon`
  Floating-point compare equal Arm’s documentation
vceqzh_f16Experimental`fp16` and `neon`
  Floating-point compare bitwise equal to zero Arm’s documentation
vcgeh_f16Experimental`fp16` and `neon`
  Floating-point compare greater than or equal Arm’s documentation
vcgezh_f16Experimental`fp16` and `neon`
  Floating-point compare greater than or equal to zero Arm’s documentation
vcgth_f16Experimental`fp16` and `neon`
  Floating-point compare greater than Arm’s documentation
vcgtzh_f16Experimental`fp16` and `neon`
  Floating-point compare greater than zero Arm’s documentation
vcleh_f16Experimental`fp16` and `neon`
  Floating-point compare less than or equal Arm’s documentation
vclezh_f16Experimental`fp16` and `neon`
  Floating-point compare less than or equal to zero Arm’s documentation
vclth_f16Experimental`fp16` and `neon`
  Floating-point compare less than Arm’s documentation
vcltzh_f16Experimental`fp16` and `neon`
  Floating-point compare less than zero Arm’s documentation
vcmla_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot90_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot90_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot90_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot90_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot90_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot90_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot180_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot180_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot180_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot180_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot180_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot180_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot270_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot270_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot270_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot270_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot270_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmla_rot270_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_f64Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_f64Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot90_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_f64Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot180_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_f64Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_lane_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_lane_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_laneq_f16Experimental`fcma` and `fp16` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcmlaq_rot270_laneq_f32Experimental`fcma` and `neon`
  Floating-point complex multiply accumulate Arm’s documentation
vcvtah_s16_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtah_s32_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtah_s64_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtah_u16_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtah_u32_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvtah_u64_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to away Arm’s documentation
vcvth_f16_s16Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_f16_s32Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_f16_s64Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_f16_u16Experimental`fp16` and `neon`
  Unsigned fixed-point convert to floating-point Arm’s documentation
vcvth_f16_u32Experimental`fp16` and `neon`
  Unsigned fixed-point convert to floating-point Arm’s documentation
vcvth_f16_u64Experimental`fp16` and `neon`
  Unsigned fixed-point convert to floating-point Arm’s documentation
vcvth_n_f16_s16Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_n_f16_s32Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_n_f16_s64Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_n_f16_u16Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_n_f16_u32Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_n_f16_u64Experimental`fp16` and `neon`
  Fixed-point convert to floating-point Arm’s documentation
vcvth_n_s16_f16Experimental`fp16` and `neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvth_n_s32_f16Experimental`fp16` and `neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvth_n_s64_f16Experimental`fp16` and `neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvth_n_u16_f16Experimental`fp16` and `neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvth_n_u32_f16Experimental`fp16` and `neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvth_n_u64_f16Experimental`fp16` and `neon`
  Floating-point convert to fixed-point, rounding toward zero Arm’s documentation
vcvth_s16_f16Experimental`fp16` and `neon`
  Floating-point convert to signed fixed-point Arm’s documentation
vcvth_s32_f16Experimental`fp16` and `neon`
  Floating-point convert to signed fixed-point Arm’s documentation
vcvth_s64_f16Experimental`fp16` and `neon`
  Floating-point convert to signed fixed-point Arm’s documentation
vcvth_u16_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned fixed-point Arm’s documentation
vcvth_u32_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned fixed-point Arm’s documentation
vcvth_u64_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned fixed-point Arm’s documentation
vcvtmh_s16_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding towards minus infinity Arm’s documentation
vcvtmh_s32_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding towards minus infinity Arm’s documentation
vcvtmh_s64_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding towards minus infinity Arm’s documentation
vcvtmh_u16_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding towards minus infinity Arm’s documentation
vcvtmh_u32_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding towards minus infinity Arm’s documentation
vcvtmh_u64_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding towards minus infinity Arm’s documentation
vcvtnh_s16_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to even Arm’s documentation
vcvtnh_s32_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to even Arm’s documentation
vcvtnh_s64_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to nearest with ties to even Arm’s documentation
vcvtnh_u16_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtnh_u32_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtnh_u64_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to nearest with ties to even Arm’s documentation
vcvtph_s16_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to plus infinity Arm’s documentation
vcvtph_s32_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to plus infinity Arm’s documentation
vcvtph_s64_f16Experimental`fp16` and `neon`
  Floating-point convert to integer, rounding to plus infinity Arm’s documentation
vcvtph_u16_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation
vcvtph_u32_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation
vcvtph_u64_f16Experimental`fp16` and `neon`
  Floating-point convert to unsigned integer, rounding to plus infinity Arm’s documentation
vdivh_f16Experimental`fp16` and `neon`
  Divide Arm’s documentation
vdup_n_f16Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Create a new vector with all lanes set to a value Arm’s documentation
vduph_lane_f16Experimental`fp16` and `neon`
  Set all vector lanes to the same value Arm’s documentation
vduph_laneq_f16Experimental`fp16` and `neon`
  Extract an element from a vector Arm’s documentation
vdupq_n_f16Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Create a new vector with all lanes set to a value Arm’s documentation
vfma_n_f16Experimental`fp16` and `neon`
  Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation
vfmah_f16Experimental`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmah_lane_f16Experimental`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmah_laneq_f16Experimental`fp16` and `neon`
  Floating-point fused multiply-add to accumulator Arm’s documentation
vfmaq_n_f16Experimental`fp16` and `neon`
  Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation
vfms_n_f16Experimental`fp16` and `neon`
  Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation
vfmsh_f16Experimental`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsh_lane_f16Experimental`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsh_laneq_f16Experimental`fp16` and `neon`
  Floating-point fused multiply-subtract from accumulator Arm’s documentation
vfmsq_n_f16Experimental`fp16` and `neon`
  Floating-point fused Multiply-Subtract from accumulator. Arm’s documentation
vget_lane_f16ExperimentalLittle-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Duplicate vector element to scalar Arm’s documentation
vgetq_lane_f16ExperimentalLittle-endian and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Duplicate vector element to scalar Arm’s documentation
vld1_dup_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load one single-element structure and replicate to all lanes of one register Arm’s documentation
vld1_f16⚠Experimental`fp16` and `neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f16_x2⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f16_x3⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_f16_x4⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load one single-element structure to one lane of one register Arm’s documentation
vld1q_dup_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load one single-element structure and replicate to all lanes of one register Arm’s documentation
vld1q_f16⚠Experimental`fp16` and `neon`
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f16_x2⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f16_x3⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_f16_x4⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load multiple single-element structures to one, two, three, or four registers Arm’s documentation
vld1q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Load one single-element structure to one lane of one register Arm’s documentation
vld2_dup_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load multiple 2-element structures to two registers Arm’s documentation
vld2q_dup_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 2-element structure and replicate to all lanes of two registers Arm’s documentation
vld2q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load multiple 2-element structures to two registers Arm’s documentation
vld3_dup_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation
vld3_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation
vld3_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load multiple 3-element structures to two registers Arm’s documentation
vld3q_dup_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation
vld3q_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 3-element structure and replicate to all lanes of two registers Arm’s documentation
vld3q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load multiple 3-element structures to two registers Arm’s documentation
vld4_dup_f16⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation
vld4_f16⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation
vld4_lane_f16⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load multiple 4-element structures to two registers Arm’s documentation
vld4q_dup_f16⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation
vld4q_f16⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load single 4-element structure and replicate to all lanes of two registers Arm’s documentation
vld4q_lane_f16⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Load multiple 4-element structures to two registers Arm’s documentation
vldap1_lane_p64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vldap1_lane_s64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vldap1_lane_u64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vldap1q_lane_f64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vldap1q_lane_p64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vldap1q_lane_s64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vldap1q_lane_u64⚠Experimental`neon` and `rcpc3`
  Load-acquire RCpc one single-element structure to one lane of one register Arm’s documentation
vluti2_lane_f16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_lane_p8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_lane_p16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_lane_s8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_lane_s16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_lane_u8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_lane_u16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_f16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_p8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_p16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_s8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_s16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_u8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2_laneq_u16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_f16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_p8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_p16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_s8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_s16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_u8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_lane_u16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_f16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_p8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_p16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_s8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_s16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_u8⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti2q_laneq_u16⚠Experimental`lut` and `neon`
  Lookup table read with 2-bit indices Arm’s documentation
vluti4q_lane_f16_x2⚠Experimental`fp16` and `lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_lane_p8⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_lane_p16_x2⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_lane_s8⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_lane_s16_x2⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_lane_u8⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_lane_u16_x2⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_f16_x2⚠Experimental`fp16` and `lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_p8⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_p16_x2⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_s8⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_s16_x2⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_u8⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vluti4q_laneq_u16_x2⚠Experimental`lut` and `neon`
  Lookup table read with 4-bit indices Arm’s documentation
vmaxh_f16Experimental`fp16` and `neon`
  Maximum (vector) Arm’s documentation
vmaxnmh_f16Experimental`fp16` and `neon`
  Floating-point Maximum Number Arm’s documentation
vmaxnmv_f16Experimental`fp16` and `neon`
  Floating-point maximum number across vector Arm’s documentation
vmaxnmvq_f16Experimental`fp16` and `neon`
  Floating-point maximum number across vector Arm’s documentation
vmaxv_f16Experimental`fp16` and `neon`
  Floating-point maximum number across vector Arm’s documentation
vmaxvq_f16Experimental`fp16` and `neon`
  Floating-point maximum number across vector Arm’s documentation
vminh_f16Experimental`fp16` and `neon`
  Minimum (vector) Arm’s documentation
vminnmh_f16Experimental`fp16` and `neon`
  Floating-point Minimum Number Arm’s documentation
vminnmv_f16Experimental`fp16` and `neon`
  Floating-point minimum number across vector Arm’s documentation
vminnmvq_f16Experimental`fp16` and `neon`
  Floating-point minimum number across vector Arm’s documentation
vminv_f16Experimental`fp16` and `neon`
  Floating-point minimum number across vector Arm’s documentation
vminvq_f16Experimental`fp16` and `neon`
  Floating-point minimum number across vector Arm’s documentation
vmmlaq_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  8-bit integer matrix multiply-accumulate Arm’s documentation
vmmlaq_u32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  8-bit integer matrix multiply-accumulate Arm’s documentation
vmov_n_f16Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Duplicate element to vector Arm’s documentation
vmovq_n_f16Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Duplicate element to vector Arm’s documentation
vmul_n_f16Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector multiply by scalar Arm’s documentation
vmulh_f16Experimental`fp16` and `neon`
  Add Arm’s documentation
vmulh_lane_f16Experimental`fp16` and `neon`
  Floating-point multiply Arm’s documentation
vmulh_laneq_f16Experimental`fp16` and `neon`
  Floating-point multiply Arm’s documentation
vmulq_n_f16Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Vector multiply by scalar Arm’s documentation
vmulx_n_f16Experimental`fp16` and `neon`
  Vector multiply by scalar Arm’s documentation
vmulxh_f16Experimental`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulxh_lane_f16Experimental`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulxh_laneq_f16Experimental`fp16` and `neon`
  Floating-point multiply extended Arm’s documentation
vmulxq_n_f16Experimental`fp16` and `neon`
  Vector multiply by scalar Arm’s documentation
vnegh_f16Experimental`fp16` and `neon`
  Negate Arm’s documentation
vrecpeh_f16Experimental`fp16` and `neon`
  Reciprocal estimate. Arm’s documentation
vrecpsh_f16Experimental`fp16` and `neon`
  Floating-point reciprocal step Arm’s documentation
vrecpxh_f16Experimental`fp16` and `neon`
  Floating-point reciprocal exponent Arm’s documentation
vrnd32x_f32Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation
vrnd32x_f64Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation
vrnd32xq_f32Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation
vrnd32xq_f64Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer, using current rounding mode Arm’s documentation
vrnd32z_f32Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer toward zero Arm’s documentation
vrnd32z_f64Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer toward zero Arm’s documentation
vrnd32zq_f32Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer toward zero Arm’s documentation
vrnd32zq_f64Experimental`frintts` and `neon`
  Floating-point round to 32-bit integer toward zero Arm’s documentation
vrnd64x_f32Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation
vrnd64x_f64Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation
vrnd64xq_f32Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation
vrnd64xq_f64Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer, using current rounding mode Arm’s documentation
vrnd64z_f32Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer toward zero Arm’s documentation
vrnd64z_f64Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer toward zero Arm’s documentation
vrnd64zq_f32Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer toward zero Arm’s documentation
vrnd64zq_f64Experimental`frintts` and `neon`
  Floating-point round to 64-bit integer toward zero Arm’s documentation
vrndah_f16Experimental`fp16` and `neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrndh_f16Experimental`fp16` and `neon`
  Floating-point round to integral, to nearest with ties to away Arm’s documentation
vrndih_f16Experimental`fp16` and `neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrndmh_f16Experimental`fp16` and `neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndnh_f16Experimental`fp16` and `neon`
  Floating-point round to integral, toward minus infinity Arm’s documentation
vrndph_f16Experimental`fp16` and `neon`
  Floating-point round to integral, toward plus infinity Arm’s documentation
vrndxh_f16Experimental`fp16` and `neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vrsqrteh_f16Experimental`fp16` and `neon`
  Reciprocal square-root estimate. Arm’s documentation
vrsqrtsh_f16Experimental`fp16` and `neon`
  Floating-point reciprocal square root step Arm’s documentation
vscale_f16Experimental`fp8` and `neon`
  Multi-vector floating-point adjust exponent Arm’s documentation
vscale_f32Experimental`fp8` and `neon`
  Multi-vector floating-point adjust exponent Arm’s documentation
vscaleq_f16Experimental`fp8` and `neon`
  Multi-vector floating-point adjust exponent Arm’s documentation
vscaleq_f32Experimental`fp8` and `neon`
  Multi-vector floating-point adjust exponent Arm’s documentation
vscaleq_f64Experimental`fp8` and `neon`
  Multi-vector floating-point adjust exponent Arm’s documentation
vset_lane_f16ExperimentalLittle-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Insert vector element from another vector element Arm’s documentation
vsetq_lane_f16ExperimentalLittle-endian and `fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Insert vector element from another vector element Arm’s documentation
vsm3partw1q_u32Experimental`neon` and `sm4`
  SM3PARTW1 Arm’s documentation
vsm3partw2q_u32Experimental`neon` and `sm4`
  SM3PARTW2 Arm’s documentation
vsm3ss1q_u32Experimental`neon` and `sm4`
  SM3SS1 Arm’s documentation
vsm3tt1aq_u32Experimental`neon` and `sm4`
  SM3TT1A Arm’s documentation
vsm3tt1bq_u32Experimental`neon` and `sm4`
  SM3TT1B Arm’s documentation
vsm3tt2aq_u32Experimental`neon` and `sm4`
  SM3TT2A Arm’s documentation
vsm3tt2bq_u32Experimental`neon` and `sm4`
  SM3TT2B Arm’s documentation
vsm4ekeyq_u32Experimental`neon` and `sm4`
  SM4 key Arm’s documentation
vsm4eq_u32Experimental`neon` and `sm4`
  SM4 encode Arm’s documentation
vsqrth_f16Experimental`fp16` and `neon`
  Floating-point round to integral, using current rounding mode Arm’s documentation
vst1_f16⚠Experimental`fp16` and `neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1_f16_x2⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f16_x3⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_f16_x4⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst1q_f16⚠Experimental`fp16` and `neon`
  Store multiple single-element structures from one, two, three, or four registers. Arm’s documentation
vst1q_f16_x2⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f16_x3⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_f16_x4⚠Experimental`fp16` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple single-element structures to one, two, three, or four registers Arm’s documentation
vst1q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM64EC
  Store multiple single-element structures from one, two, three, or four registers Arm’s documentation
vst2_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 2-element structures from two registers Arm’s documentation
vst2_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 2-element structures from two registers Arm’s documentation
vst2q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 2-element structures from two registers Arm’s documentation
vst3_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 3-element structures from three registers Arm’s documentation
vst3_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 3-element structures from three registers Arm’s documentation
vst3q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 3-element structures from three registers Arm’s documentation
vst4_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 4-element structures from four registers Arm’s documentation
vst4_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 4-element structures from four registers Arm’s documentation
vst4q_lane_f16⚠Experimental`neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`) and non-ARM and non-ARM64EC
  Store multiple 4-element structures from four registers Arm’s documentation
vstl1_lane_f64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1_lane_p64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1_lane_s64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1_lane_u64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1q_lane_f64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1q_lane_p64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1q_lane_s64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vstl1q_lane_u64⚠Experimental`neon` and `rcpc3`
  Store-Release a single-element structure from one lane of one register. Arm’s documentation
vsubh_f16Experimental`fp16` and `neon`
  Subtract Arm’s documentation
vsudot_lane_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with signed and unsigned integers Arm’s documentation
vsudot_laneq_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with signed and unsigned integers Arm’s documentation
vsudotq_lane_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with signed and unsigned integers Arm’s documentation
vsudotq_laneq_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with signed and unsigned integers Arm’s documentation
vusdot_lane_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with unsigned and signed integers Arm’s documentation
vusdot_laneq_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with unsigned and signed integers Arm’s documentation
vusdot_s32ExperimentalLittle-endian and `i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product vector form with unsigned and signed integers Arm’s documentation
vusdotq_lane_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with unsigned and signed integers Arm’s documentation
vusdotq_laneq_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product index form with unsigned and signed integers Arm’s documentation
vusdotq_s32ExperimentalLittle-endian and `i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Dot product vector form with unsigned and signed integers Arm’s documentation
vusmmlaq_s32Experimental`i8mm` and `neon` and (AArch64 or ARM or ARM64EC) and (AArch64 or ARM64EC or `v7`)
  Unsigned and signed 8-bit integer matrix multiply-accumulate Arm’s documentation