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sscblif - Esterel blif code producer for Esterel v5_92
sscblif
[options] file.ssc
The sscblif code producer takes as input
a circuit described in ssc format (Sorted Soft Code Format) and translates
it into a circuit described in blif (Berkeley Logic Interchange Format).
When used without any options, sscblif only translates circuits generated
from Pure Esterel programs with possible counters. With -soft option circuits
from Full Esterel programs are accepted. The result is a circuit describing
the control of the program. It may be used by the blifssc processor to
generate optimized ssc code. The produced circuits may be optimized (see
option -O). In that case, sscblif calls blifopt-1.2. This program will call
the optimizer sis-1.2. The user can use his/her own optimizer by setting
the shell SSCBLIF_OPT variable to the new program name. sscblif will call
this new one instead of blifopt-1.2. The options must be the same.
- -version
- Print the version name on the standard output stream and terminate, ignoring
all other arguments.
- -access
- Print various informations about the compilation
of the processor on the standard output stream and terminate, ignoring
all other arguments.
- -info
- Print various informations about the
processor compilation on the standard error output stream and terminate,
ignoring all other arguments.
- -s
- Silent mode. No output is generated.
- -v
- Verbose
mode.
- -B name
name denotes the output file base name, The suffix ".opt.blif"
is added automatically. If this option and the -D option are omitted, the
name sscblif_out.opt.blif is used.
- -D directory
- Specifies a directory where
the output file(s) will be placed. The default is the current directory.
- -hierarchy
- Decompose the circuit into subcircuits. Use this option to optimize
large circuits.
- -K
- Keeps intermediate files.
- -O
- Call the optimizer. Default
optimizations improves speed of Pure Esterel programs and improves area
in case of control extraction (see -soft option). Optimizations can be controlled
with the following options:
- -area
- Optimizes using area optimization.
- -h_speed
- Optimizes using speed optimization only.
- -speed
- Optimizes using speed optimization
and performs technology mapping to Xilinx.
- -script
- filename
Specify to use the file filename as optimization script. The name of the
script must be a full file name. See sis(1)
for writing scripts.
- -soft
- Specify
to extract the control of the circuit.
- -makefile
- sscblif produces a makefile
when optimization is run and deletes it unless the -K option is specified.
The -makefile option allows to obtain this makefile without running the
optimization.
- -w
- suppress any warning.
- -W
- print out any warning.
If
foo.ssc is generated from a Pure Esterel program, the command: sscblif foo.ssc
-B foo
produce the file foo.blif. If the original program contains static
counters (ie counters with a known value at compile time, such as await
4 I), then two files are produced:
- foo.ctl.blif
- this file contains the program
control.
- foo.blif
- this is the main circuit that contains the description
of the needed counters and the call to the program control circuit.
If foo.ssc
is generated from a general Esterel program, then sscblif can only extracts
the program control logic. It must be called as follows:
sscblif -soft foo.ssc
In this case, two files are generated:
- foo.blif
- the actual circuit from
the program control.
- foo.ctbl
- this file describes the dependencies between
the actions within the Esterel program and will be used when rebuild a
.ssc file from a .blif file. See blifssc(1)
.
The command:
sscblif -O foo.ssc
-B foo
will produce an optimized circuit always in the file foo.opt.blif.
Finally, assuming that foo.ssc is generated from a Full Esterel program,
the following command:
sscblif foo.ssc -B foo -soft -hierarchy -O -script /tmp/foo.script
will extract the control of the circuit and decompose it in sub-circuits.
Each sub-circuit will be optimized using the user script /tmp/foo.script.
inputoutput signals receive a special treatment since an inputoutput
wire cannot be expressed in blif. Thus, for each inputoutput signal, say
X, two wires are generated: one for the input and one for the output. The
naming convention is as follow: the input wire is named X_IO_I while the
output signal is named X_IO_O. Be careful to not already have a signal
with one of this name since no checks are performed.
A make file
is generated when optimizing. The base name of this file depends on the
-B option and its suffix is .make. With -soft option another file is generated
with suffix .ctbl. This file will be used by the blifssc processor.
The Esterel v5_92 Documentation.
esterel(1)
, scssc(1)
, blifopt(1)
, sis(1)
, blifssc(1)
Ecole
des Mines de Paris (CMA) and INRIA.
Author: Francois-Xavier Fornari.
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